參數(shù)資料
型號(hào)： TLV320ALC23
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC
中文描述： 評(píng)估平臺(tái)為TLV320ALC23 DAC的立體聲音頻編解碼器和立體聲TLV230DAC23
文件頁(yè)數(shù)： 31/46頁(yè)
文件大?。?/td> 452K
代理商： TLV320ALC23
SLAS428 AUGUST 2004
www.ti.com
31
REGISTER 04H: Audio Control 2
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15
KCLEN
R/W
0
Keyclick Enable
0 => Keyclick disabled
1 => Keyclick enabled
Note: This bit is automatically cleared after giving out the keyclick signal length equal to the
programmed value.
D14D12
KCLAC
R/W
100
Keyclick Amplitude Control
000 => Lowest amplitude
100 => Medium amplitude
111 => Highest amplitude
D11
Reserved
R/W
0
Reserved
Note: Only write a 0 to this bit
D10D8
KCLFRQ
R/W
100
Keyclick Frequency
000 => 62.5 Hz
001 => 125 Hz
010 => 250 Hz
011 => 500 Hz
100 => 1 kHz
101 => 2 kHz
110 => 4 kHz
111 => 8 kHz
D7D4
KCLLN
R/W
0001
Keyclick Length
0000 => 2 periods key click
0001 => 4 periods key click
0010 => 6 periods key click
1110 => 30 periods key click
1111 => 32 periods key click
D3
DLGAF
R
0
DAC Left Channel PGA Flag ( Read Only )
0 => Gain applied /= PGA register setting
1 => Gain applied = PGA register setting
Note: This flag indicates when the soft-stepping for DAC left channel is completed
DAC Right Channel PGA Flag ( Read Only )
0 => Gain applied /= PGA register setting
1 => Gain applied = PGA register setting
Note: This flag indicates when the soft-stepping for DAC right channel is completed
D2
DRGAF
R
0
D1
DASTC
R/W
0
DAC Channel PGA Soft-Stepping Control
0 => 0.5dB change every LRCK
1 => 0.5dB change every 2 LRCK
D0
Reserved
R/W
0
Reserved
Note: Only write a 0 to this bit
相關(guān)PDF資料
PDF描述
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TLV320DAC23IGQE STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TLV320DAC23 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO D/A CONVERTER, 8-TO 96KHZ WITH INTERGRATED HEADPHONE AMPLIFIER
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