參數(shù)資料
型號(hào): TLV320AIC34_1
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 四通道,低功耗音頻編解碼器的便攜式音頻/電話
文件頁(yè)數(shù): 58/94頁(yè)
文件大?。?/td> 905K
代理商: TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 14:
Headset / Button Press Detection Register B
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
Stereo Output Driver Configuration A
Note: Do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used.
1: A stereo fully-differential output configuration is being used.
Button Press Detection Flag
This register is a sticky bit, and stays set to 1 after a button press has been detected, until the register is
read. On reading this register, the bit is reset to zero.
0: A button press has not been detected.
1: A button press has been detected.
Headset Detection Flag
0: A headset has not been detected.
1: A headset has been detected.
Stereo Output Driver Configuration B
Note: Do not set bits D6 and D3 both high at the same time.
0: A stereo pseudodifferential output configuration is not being used.
1: A stereo pseudodifferential output configuration is being used.
Reserved. Write only zeros to these bits.
D6
(1)
R/W
0
D5
R
0
D4
R
0
D3
(1)
R/W
0
D2–D0
R
000
(1)
Do not set D6 and D3 to 1 simultaneously.
Page 0 / Register 15:
Left-ADC PGA Gain Control Register
READ/
WRITE
R/W
RESET
VALUE
1
BIT
DESCRIPTION
D7
Left-ADC PGA Mute
0: The left-ADC PGA is not muted.
1: The left-ADC PGA is muted.
Left-ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
111 1111: Gain = 59.5 dB
D6–D0
R/W
000 0000
Page 0 / Register 16:
Right-ADC PGA Gain Control Register
READ/
WRITE
R/W
RESET
VALUE
1
BIT
DESCRIPTION
D7
Right-ADC PGA Mute
0: The right-ADC PGA is not muted.
1: The right-ADC PGA is muted.
Right-ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
111 1111: Gain = 59.5 dB
D6–D0
R/W
000 0000
58
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Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
TLV320AIC34
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