參數(shù)資料
型號(hào)： TLV320AIC34_1
廠商： Texas Instruments, Inc.
元件分類(lèi)： Codec
英文描述： FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述： 四通道，低功耗音頻編解碼器的便攜式音頻/電話(huà)
文件頁(yè)數(shù)： 54/94頁(yè)
文件大小： 905K
代理商： TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 4:
PLL Programming Register B
READ/
WRITE
R/W
RESET
VALUE
0000 01
BIT
DESCRIPTION
D7–D2
PLL J Value
0000 00: Reserved. Do not write this sequence to these register bits.
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
Reserved. Write only zeros to these bits.
D1–D0
R/W
00
Page 0 / Register 5:
PLL Programming Register C
(1)
READ/
WRITE
R/W
RESET
VALUE
0000 0000
BIT
DESCRIPTION
D7–D0
PLL D value – Eight most-significant bits of a 14-bit unsigned integer. Valid values for D are from zero to
9999, represented by a 14-bit integer located in page 0, registers 5–6. Values should not be written into
these registers that would result in a D value outside the valid range.
(1)
Note that whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
PLL Programming Register D
READ/
WRITE
R/W
RESET
VALUE
0000 00
BIT
DESCRIPTION
D7–D2
PLL D value – Six least-significant bits of a 14-bit unsigned integer. Valid values for D are from zero to
9999, represented by a 14-bit integer located in page 0, registers 5–6. Values should not be written into
these registers that would result in a D value outside the valid range.
Reserved. Write only zeros to these bits.
D1–D0
R
00
Page 0 / Register 7:
Codec Data-Path Setup Register
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
f
Setting
This register setting controls timers related to the AGC time constants.
0: f
S(ref)
= 48 kHz
1: f
S(ref)
= 44.1 kHz
ADC Dual Rate Control
0: ADC dual-rate mode is disabled.
1: ADC dual-rate mode is enabled.
Note: ADC dual-rate mode must match DAC dual-rate mode.
DAC Dual Rate Control
0: DAC dual rate mode is disabled.
1: DAC dual rate mode is enabled.
Left-DAC Data-Path Control
00: Left-DAC data path is off (muted).
01: Left-DAC data path plays left-channel input data.
10: Left-DAC data path plays right-channel input data.
11: Left-DAC data path plays mono mix of left- and right-channel input data.
Right-DAC Data Path Control
00: Right-DAC data path is off (muted).
01: Right-DAC data path plays right-channel input data.
10: Right-DAC data path plays left-channel input data.
11: Right-DAC data path plays mono mix of left- and right-channel input data.
Reserved. Write only zero to this bit.
D6
R/W
0
D5
R/W
0
D4–D3
R/W
00
D2–D1
R/W
00
D0
R/W
0
54
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Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
TLV320AIC34
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