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參數(shù)資料
型號： TLV320AIC31IRHBRG4
廠商： Texas Instruments
文件頁數(shù)： 47/84頁
文件大小： 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 34:
Left AGC Noise Gate Debounce Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D3
R/W
00000
Left AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64×1 = 64ms
01001: Debounce = 64×2 = 128ms
01010: Debounce = 64×3 = 192ms
…
11110: Debounce = 64×23 = 1472ms
11111: Debounce = 64×24 = 1536ms
D2–D0
R/W
000
Left AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1)
Time constants are valid when DRA is not enabled. The values would change when DRA is enabled
Page 0 / Register 35:
Right AGC Noise Gate Debounce Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D3
R/W
00000
Right AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64×1 = 64ms
01001: Debounce = 64×2 = 128ms
01010: Debounce = 64×3 = 192ms
…
11110: Debounce = 64×23 = 1472ms
11111: Debounce = 64×24 = 1536ms
D2–D0
R/W
00000
Right AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1)
Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
Copyright 2006–2008, Texas Instruments Incorporated
51
Product Folder Link(s): TLV320AIC31
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