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參數(shù)資料
型號： TLV320AIC31IRHBRG4
廠商： Texas Instruments
文件頁數(shù)： 45/84頁
文件大?。?/td> 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標準包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調變： 是
S/N 比，標準 ADC / DAC (db)： 92 / 100
動態(tài)范圍，標準 ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應商設備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
ELECTRICAL CHARACTERISTICS
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
At +25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, FS = 48 kHz, 16-bit audio data (unless otherwise noted).
TLV320AIC31
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
Input signal level (0 dB)
Single-ended input
0.707
VRMS
Signal-to-noise ratio,
FS = 48 kHz, 0-dB PGA gain, IN1 inputs selected
80
92
dB
A-weighted(1) (2)
and ac-shorted together
FS = 48 kHz, 1-kHz –60 dB full-scale input applied
Dynamic range, A-weighted(1) (2)
92
dB
at IN1 inputs, 0-dB PGA gain
–90
–75
dB
FS = 48 kHz, 1-kHz –2dB full-scale input applied at
THD
Total harmonic distortion
IN1 inputs, 0-dB PGA gain
0.003%
0.018%
1 kHz, 100 mVPP on AVDD, DRVDD, single-ended
46
input
Power-supply rejection ratio
dB
1 kHz, 100 mVPP on AVDD, DRVDD, differential
68
input
ADC channel separation
1 kHz, –1 dB IN2L to IN2R
–87
dB
ADC gain error
1-kHz input, 0-dB PGA gain
0.7
dB
ADC programmable gain amplifier
1-kHz input tone, RSOURCE < 50
59.5
dB
maximum gain
ADC programmable gain amplifier
0.5
dB
step size
IN1 inputs, routed to single ADC Input mix
20
attenuation = 0 dB
IN2 inputs, input mix attenuation = 0 dB
20
Input resistance
k
IN1 inputs, Input mix attenuation = –12 dB
80
IN2 inputs, Input mix attenuation = –12 dB
80
Input capacitance
IN1 inputs
10
pF
Input level control minimum
0
dB
attenuation setting
Input level control maximum
12
dB
attenuation setting
Input level control attenuation
1.5
dB
step size
ADC DIGITAL DECIMATION FILTER, FS = 48 kHz
Filter gain from 0 to 0.39 FS
±0.1
dB
Filter gain at 0.4125 FS
–0.25
dB
Filter gain at 0.45 FS
–3
dB
Filter gain at 0.5 FS
–17.5
dB
Filter gain from 0.55 FS to 64 FS
–75
dB
Filter group delay
17/FS
Sec
MICROPHONE BIAS
2.0
Bias voltage
Programmable settings, load = 750
2.25
2.5
2.75
V
AVDD – 0.2
Current sourcing
2.5 V setting
4
mA
(1)
Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2)
All performance measurements made with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
Copyright 2006–2008, Texas Instruments Incorporated
5
Product Folder Link(s): TLV320AIC31
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