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參數(shù)資料
| 型號(hào)： | TLV320AIC31IRHBRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 36/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STEREO AUDIO CODEC LP 32-VQFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | PCM 音頻接口 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 100 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 100 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 1.95 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31 296-19475-ND - MODULE EVAL FOR TLV320AIC31 |
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www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 8:
Audio Serial Data Interface Control Register A
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
D6
R/W
0
Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
D5
R/W
0
Serial Output Data Driver (DOUT) 3-state control
0: Do not 3-state DOUT when valid data is not being sent
1: 3-state DOUT when valid data is not being sent
D4
R/W
0
Bit/ Word Clock Drive Control
0:
Bit clock and word clock will not be transmitted when in master mode if codec is powered down
1:
Bit clock and word clock will continue to be transmitted when in master mode, even if codec is
powered down
D3
R/W
0
Reserved. Only write '0' to this register.
D2
R/W
0
3D Effect Control
0: Disable 3-D digital effect processing
1: Enable 3-D digital effect processing
D1-D0
R/W
00
Reserved. Only write '00' to this register
Page 0 / Register 9:
Audio Serial Data Interface Control Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
D5–D4
R/W
00
Audio Serial Data Word Length Control
00: Audio data word length = 16-bits
01: Audio data word length = 20-bits
10: Audio data word length = 24-bits
11: Audio data word length = 32-bits
D3
R/W
0
Bit Clock Rate Control
This register only has effect when bit clock is programmed as an output
0: Continuous-transfer mode used to determine master mode bit clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per frame
D2
R/W
0
DAC Re-Sync
0: Don’t Care
1:
Re-Sync Stereo DAC with Codec Interface if the group delay changes by more than ±DACFS/4.
D1
R/W
0
ADC Re-Sync
0: Don’t Care
1:
Re-Sync Stereo ADC with Codec Interface if the group delay changes by more than ±ADCFS/4.
D0
R/W
Re-Sync Mute Behavior
0: Re-Sync is done without soft-muting the channel. (ADC/DAC)
1: Re-Sync is done by internally soft-muting the channel. (ADC/DAC)
Copyright 2006–2008, Texas Instruments Incorporated
41
Product Folder Link(s): TLV320AIC31
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| TLV320AIC31IRHBT | 功能描述:接口—CODEC Lo-Pwr Ster Codec for Port Aud/Teleph RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC31IRHBT | 制造商:Texas Instruments 功能描述:IC CODEC STEREO AUDIO 32-VQFN |
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