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參數(shù)資料
型號： TLV320AIC31IRHBR
廠商： Texas Instruments
文件頁數(shù)： 40/84頁
文件大?。?/td> 0K
描述： IC STEREO AUDIO CODEC LP 32-VQFN
標(biāo)準(zhǔn)包裝： 3,000
類型： 立體聲音頻
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 100
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 296-19476-ND - KIT EVAL/DEMO FOR TLV320AIC31
296-19475-ND - MODULE EVAL FOR TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 18:
IN2L/R to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
1111
IN2L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects IN2L to the right ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: IN2L is not connected to the right ADC PGA
D3–D0
R/W
1111
IN2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects IN2R to the right ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: IN2R is not connected to right ADC PGA
Page 0 / Register 19:
IN1L to Left ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
IN1L Single-Ended vs Fully Differential Control If IN1L is selected to both left and right ADC
channels, both connections must use the same configuration (single-ended or fully-differential
mode).
0: IN1L is configured in single-ended mode
1: IN1L is configured in fully-differential mode
D6–D3
R/W
1111
IN1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects IN1L to the left ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: IN1L is not connected to the left ADC PGA
D2
R/W
0
Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1–D0
R/W
00
Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per FS
01: Left ADC PGA soft-stepping at once per two FS
10–11: Left ADC PGA soft-stepping is disabled
Copyright 2006–2008, Texas Instruments Incorporated
45
Product Folder Link(s): TLV320AIC31
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