參數(shù)資料
型號： TLV320AIC20C
廠商： Texas Instruments, Inc.
英文描述： Layout and Grounding Guidelines for TLV320AIC2x
中文描述： 為TLV320AIC2x布局和接地指南
文件頁數(shù)： 2/46頁
文件大小： 452K
代理商： TLV320AIC20C
SLAS428 AUGUST 2004
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE RANGE
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
Tubes, 74
Tape and Reel, 3000
TLV320DAC26
QFN-32
RHB
40
°
C to 85
°
C
TLV320DAC26IRHB
TLV320DAC26IRHBR
PIN ASSIGNMENTS
QFN
(TOP VIEW)
31 30 29 28 27
9 10
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DRVDD
VGND
DRVSS
HPL
AVDD
NC
NC
NC
DVSS
IOVDD
MCLK
SCLK
MISO
MOSI
SS
NC
32
26
11 12 13 14 15
M
M
A
N
A
D
B
N
D
P
L
R
16
H
25
N
N
N
DAC26
Terminal Functions
QFN
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
DESCRIPTION
QFN
PIN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
DESCRIPTION
DVSS
IOVDD
MCLK
SCLK
MISO
MOSI
SS
NC
MICBIAS
MICIN
AUX
NC
NC
NC
AVSS
NC
Digital core and IO ground
IO supply
Master clock
SPI serial clock input
SPI serial data output
SPI serial data input
SPI slave select input
No connect
Microphone bias voltage
Microphone input
Auxiliary input
No connect
No connect
No connect
Analog ground
No connect
NC
NC
NC
AVDD
HPL
DRVSS
VGND
DRVDD
HPR
RESET
LRCK
PWD
DIN
NC
BCLK
DVDD
No connect
No connect
No connect
Analog power supply
Left channel audio output
Speaker ground
Virtual ground for audio output
Speaker /PLL supply
Right channel audio output
Device reset
Audio DAC word-clock
Hardware powerdown
Audio data input
No connect
Audio bitclock
Digital core supply
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