參數(shù)資料
型號(hào): TLV320AIC10PFB
廠商: Texas Instruments, Inc.
英文描述: ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles
中文描述: 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁數(shù): 31/46頁
文件大?。?/td> 452K
代理商: TLV320AIC10PFB
SLAS428 AUGUST 2004
www.ti.com
31
REGISTER 04H: Audio Control 2
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15
KCLEN
R/W
0
Keyclick Enable
0 => Keyclick disabled
1 => Keyclick enabled
Note: This bit is automatically cleared after giving out the keyclick signal length equal to the
programmed value.
D14D12
KCLAC
R/W
100
Keyclick Amplitude Control
000 => Lowest amplitude
100 => Medium amplitude
111 => Highest amplitude
D11
Reserved
R/W
0
Reserved
Note: Only write a 0 to this bit
D10D8
KCLFRQ
R/W
100
Keyclick Frequency
000 => 62.5 Hz
001 => 125 Hz
010 => 250 Hz
011 => 500 Hz
100 => 1 kHz
101 => 2 kHz
110 => 4 kHz
111 => 8 kHz
D7D4
KCLLN
R/W
0001
Keyclick Length
0000 => 2 periods key click
0001 => 4 periods key click
0010 => 6 periods key click
1110 => 30 periods key click
1111 => 32 periods key click
D3
DLGAF
R
0
DAC Left Channel PGA Flag ( Read Only )
0 => Gain applied /= PGA register setting
1 => Gain applied = PGA register setting
Note: This flag indicates when the soft-stepping for DAC left channel is completed
DAC Right Channel PGA Flag ( Read Only )
0 => Gain applied /= PGA register setting
1 => Gain applied = PGA register setting
Note: This flag indicates when the soft-stepping for DAC right channel is completed
D2
DRGAF
R
0
D1
DASTC
R/W
0
DAC Channel PGA Soft-Stepping Control
0 => 0.5dB change every LRCK
1 => 0.5dB change every 2 LRCK
D0
Reserved
R/W
0
Reserved
Note: Only write a 0 to this bit
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