參數(shù)資料
型號(hào): TLV320AIC10PFB
廠商: Texas Instruments, Inc.
英文描述: ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles
中文描述: 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁(yè)數(shù): 10/46頁(yè)
文件大?。?/td> 452K
代理商: TLV320AIC10PFB
SLAS428 AUGUST 2004
www.ti.com
10
LRCK/ADWS
BCLK
DIN
tL(BCLK)
th(DI)
tS(WS)
tH(BCLK)
th(WS)
tP(BCLK)
th(WS)
tS(WS)
Figure 4. DSP Timing in Slave Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 4)
All specifications at 25
°
C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V
MIN
35
IOVDD = 3.3 V
MIN
35
UNITS
MAX
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
ts(DI)
th(DI)
tr
tf
(1)These parameters are based on characterization and are not tested in production.
BCLK high period
ns
BCLK low period
35
35
ns
LRCK setup time
6
6
ns
LRCK hold time
6
6
ns
DIN setup time
6
6
ns
DIN hold time
6
6
ns
Rise time
5
4
ns
Fall time
5
4
ns
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