參數(shù)資料
型號(hào): TLV320AIC10PFB
廠商: Texas Instruments, Inc.
英文描述: ECONOLINE: RSS & RSD - 1kVDC and 3KVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 85%- SMD5, SMD8, SMD10 and SMD12 case styles
中文描述: 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁數(shù): 14/46頁
文件大?。?/td> 452K
代理商: TLV320AIC10PFB
SLAS428 AUGUST 2004
www.ti.com
14
RIGHT-JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the BCLK preceding the falling edge of
LRCK. Similarly, the LSB of the right channel is valid on the rising edge of the BCLK preceding the rising edge of LRCK.
BCLK
LRCK
DIN/
n
n1
1
0
0
n
n1
1
0
LSB
MSB
n2
2
2
n2
1/fs
Left Channel
Right Channel
Figure 9. Timing Diagram for Right-Justified Mode
LEFT-JUSTIFIED MODE
In leftjustified mode, the MSB of the right channel is valid on the rising edge of the BCLK, following the falling edge of
ADWS or LRCK. Similarly the MSB of the left channel is valid on the rising edge of the BCLK following the rising edge of
ADWS or LRCK.
BCLK
LRCK
DIN
n
n1
1
0
n
n1
1
0
LSB
MSB
n
n1
n2
2
n2
2
1/fs
Left Channel
Right Channel
Figure 10. Timing Diagram for Left-Justified Mode
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