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參數(shù)資料
| 型號： | TLV1548QDBREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, SSOP-20 |
| 文件頁數(shù)： | 32/35頁 |
| 文件大?。?/td> | 686K |
| 代理商： | TLV1548QDBREP |
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TLV1548EP
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS171A JUNE 2003 REVISED DECEMBER 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DSP interface
The TLV1548 can also interface with a DSP, from the TMS320 family for example, through a serial port. The
analog-to-digital converter (ADC) serves as a slave device where the DSP supplies FS and the serial I/O CLK.
Transmit and receive operations are concurrent. The falling edge of FS must occur no later than seven I/O CLK
periods after the falling edge of CS.
DSP I/O cycles differ from microprocessor I/O cycles in the following ways:
D When interfaced with a DSP, the output data MSB is available afterFS↓. The remaining output data changes
on the rising edge of I/O CLK. The input data is sampled on the first four falling edges of I/O CLK after FS
↓
and when INV CLK is high, or the first four rising edges of I/O CLK after FS
↓ and when INV CLK is low. This
operation is inverted when interfaced with a microprocessor.
D A new DSP I/O cycle is started on the rising edge of I/O CLK after the rising edge of FS. The internal state
machine is reset on each falling edge of I/O CLK when FS is high. This operation is opposite when interfaced
with a microprocessor.
D The TLV1548 supports a 16-clock cycle when interfaced with a DSP. The output data is padded with six
trailing zeros when it is operated in DSP mode.
Table 2. TLV1548 Serial Interface Modes
I/O
INTERFACE MODE
I/O
MICROPROCESSOR ACTION
DSP ACTION
CS
↓
Initializes counter
Samples state of FS
CS
↑
Resets state machine and disable I/O
Disables I/O
FS
Connects to VCC
Connects to DSP FSX output
Initializes the state machine at each CLK
↓ after FS↑
Starts a new cycle at each CLK
↑ following the initialization
(initializes the counter)
I/O CLK
Starts sampling of the analog input started at fourth I/O CLK
↑
Conversion started at tenth I/O CLK
↑
Starts sampling of the analog input at fourth I/O CLK
↓
Starts sampling of the analog input at tenth I/O CLK
↓
DATA IN
Samples input data on I/O CLK
↑ (INV CLK high)
Samples input data on I/O CLK
↓ (INV CLK low)
Samples input data at I/O CLK
↓ (INV CLK high)
Samples input data at I/O CLK
↑ (INV CLK low)
DATA OUT
Makes MSB available on CS
↓
Changes remaining data on I/O CLK
↓
Makes MSB available FS
↓
Changes remaining data at each following I/O CLK
↑ after
FS
↓
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| TLV1548QDBRG4Q1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10B 85kSPS ADC Ser. Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1548QDBRQ1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10B Analog/Digital Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1549 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1549C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV1549CD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 3.3V 10bit A/D RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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