參數(shù)資料
型號： TLV1548QDBREP
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： GREEN, SSOP-20
文件頁數(shù)： 25/35頁
文件大?。?/td> 686K
代理商： TLV1548QDBREP
TLV1548EP
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS171A JUNE 2003 REVISED DECEMBER 2003
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATIONS INFORMATION
Rs
ri
VS
VC
55 pF MAX
1 k
Driving Source
TLV1548
Ci
VI
VI = Input Voltage at AIN
VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance (MUX on Resistance)
Ci = Input Capacitance
VC= Capacitance Charging Voltage
Driving source requirements:
Noise and distortion for the source must be equivalent to the resolution of the converter.
Rs must be real at the input frequency.
Figure 40. Equivalent Input Circuit Including the Driving Source
maximum conversion throughput
For a supply voltage at 5 V, if the source impedance is less than 1 k
, this equates to a minimum sampling
time tch(0.5 LSB) of 0.84 s. Since the sampling time requires six I/O clocks, the fastest I/O clockfrequency is
6/tch = 7.18 MHz. The minimal total cycle time is given as:
tc = taddress + tsample + tconv + td(EOC↑ CS↓)
= 0.56
s + 0.84 s + 10 s + 0.1 s
= 11.5
s
A maximum throughput of 87 KSPS. The throughput can be even higher with a smaller source impedance.
When source impedance is 100
, the minimum sampling time is 0.46 s. The maximum I/O clock frequency
possible is almost 13 MHz. Then 10 MHz clock (maximum I/O CLK for TLV1548) can be used. The minimal total
cycle time is:
tc = taddress + tsample + tconv + td(EOC↑ CS↓)
= 4
× 1/f + 0.46 s + 10 s + 0.1 s
= 0.4
s + 0.46 s + 10 s + 0.1 s
= 10.96
s
The maximum throughput is 1/10.96
s = 91 KSPS for this case.
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