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參數(shù)資料
| 型號： | TLV1548QDBREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, SSOP-20 |
| 文件頁數(shù)： | 23/35頁 |
| 文件大小： | 686K |
| 代理商： | TLV1548QDBREP |
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TLV1548EP
LOW VOLTAGE 10BIT ANALOGTODIGITAL CONVERTER
WITH SERIAL CONTROL AND 8 ANALOG INPUTS
SGLS171A JUNE 2003 REVISED DECEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
A0A3
A4A7
14
58
I
Analog inputs. The analog inputs are internally multiplexed. (For a source impedance greater than
1 k
, the asynchronous start should be used to increase the sampling time.)
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA IN, DATA
OUT, and I/O CLK within the maximum setup time. A low-to-high transition disables DATA IN, DATA OUT, and I/O
CLK within the setup time.
CSTART
9
I
Sampling/conversion start control. CSTART controls the start of the sampling of an analog input from a selected
multiplex channel. A high-to-low transition starts the sampling of the analog input signal. A low-to-high transition puts
the sample-and-hold function in hold mode and starts the conversion. CSTART is independent from I/O CLK and
works when CS is high. The low CSTART duration controls the duration of the sampling cycle for the switched
capacitor array. CSTART is tied to VCC if not used.
DATA IN
17
I
Serial data input. The 4-bit serial data selects the desired analog input and test voltage to be converted next in a
normal cycle. These bits can also set the conversion rate and enable the power-down mode.
When operating in the microprocessor mode, the input data is presented MSB first and is shifted in on the first four
rising (INV CLK = VCC) or falling (INV CLK = GND) edges of I/O CLK (after CS↓).
When operating in the DSP mode, the input data is presented MSB first and is shifted in on the first four falling (INV
CLK = VCC) or rising (INV CLK = GND) edges of I/O CLK (after FS↓).
After the four input data bits have been read into the input data register, DATA IN is ignored for the remainder of the
current conversion period.
DATA OUT
16
O
Three-state serial output of the A/D conversion result. DATA OUT is in the high-impedance state when CS is high
and active when CS is low or after FS
↓ (in DSP mode). With a valid CS signal, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB or LSB value of the previous
conversion result. DATA OUT changes on the falling (microprocessor mode) or rising (DSP mode) edge of I/O CLK.
EOC
19
O
End of conversion. EOC goes from a high to a low logic level on the tenth rising (microprocessor mode) or tenth
falling (DSP mode) edge of I/O CLK and remains low until the conversion is complete and data is ready for transfer.
EOC can also indicate that the converter is busy.
FS
12
I
DSP frame synchronization input. FS indicates the start of a serial data frame into or out of the device. FS is tied
to VCC when interfacing the device with a microprocessor.
GND
10
Ground return for internal circuitry. All voltage measurements are with respect to GND, unless otherwise noted.
INV CLK
11
I
Inverted clock input. INV CLK is tied to GND when an inverted I/O CLK is used as the source of the input clock. This
affects both microprocessor and DSP interfaces. INV CLK is tied to VCC if I/O CLK is not inverted. INV CLK can also
invoke a built-in test mode.
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