參數(shù)資料
型號(hào): TLE6712
廠商: INFINEON TECHNOLOGIES AG
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: PLASTIC, DSO-24
文件頁(yè)數(shù): 6/48頁(yè)
文件大?。?/td> 386K
代理商: TLE6712
TLE 6712
Company Confidential
14
V 1.61 2001-07-13
the result of the gain 10/30 amplifier is out of range. To measure the seat belt switch
resistance the voltage drop across pin MSR is multiplied by two and is reported to pin
MO. Furthermore, voltage on pin SQHx can be measured to provide the diagnostics of
the buckle switch (see Figure 6).
The measurement for each squib is activated separately, but the analog output signals
on pins MO and MSR are common.
The pins MO and MSR of several ASICs can be connected together. Therefore the
external resistor on pin MSR is only used once and is common for all IC's.
2.4.2
Squib Leakage Measurement
The leakage resistance measurement circuit can be addressed by the SPI command
1XXX
H (see Chapter 3.4.4). The programmed current for the leakage measurement
I
MCA is derived from a 1:1 current mirror to ILL and ILH. During leakage resistor
measurement, the pin MCA will be regulated to
V
S/3. The measurement current will be
calculated as
I
MCA = VS /(3 x RMCA). As menioned in the squib resistance description, the
resistor
R
MCA is fixed at 4 k to 6 k. This functional block is illustrated in the Figure 7.
(
I
LL is the leakage to ground and ILH is the leakage to battery)
The voltage drop
V
LL across the leakage resistor RLL is the drop between pin SQHx and
ground.
V
LL is calculated as follows:
The voltage drop
V
LH across the leakage resistor RLH is the drop between pin SQHx
(x = 1, 2) and
V
S. VLH is calculated as follows:
If the voltage drop across leakage resistance to ground or the drop to
V
S falls below a
quarter of
V
S the window comparator is switched by the leakage and reports it to pin MO.
As both voltages drop across the leakage resistors (R
LL, RLH) are the same, the
calculation is only shown for
R
LL.
IMCA
VS
3
RMCA
×
-----------------------
ILL
ILH
==
=
VLL
ILL RLL
×
VS
3
RMCA
×
-----------------------
RLL
×
=
VLH
ILH RLH
×
VS
3
RMCA
×
-----------------------
RLH
×
=
VLL
1
4
---
VS
VLH VS
3
4
---
VS
1
4
---
VS
=
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