參數(shù)資料
型號: TLE6712
廠商: INFINEON TECHNOLOGIES AG
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: PLASTIC, DSO-24
文件頁數(shù): 45/48頁
文件大?。?/td> 386K
代理商: TLE6712
TLE 6712
Company Confidential
6
V 1.61 2001-07-13
2
Circuit Description
2.1
Internal Supply
Supply principles:
The design of the internal supply is such that increasing or decreasing of the supply
voltages
V
FV12, VBoost, VCHP, VS, VCC5 causes no unintended firing of the squibs.
Squib failures such as shorts to ground or battery do not have an influence on other
chip functions.
An open ground connection does not cause unwanted firing.
2.1.1
Logic Supply
V
CC5
Input pin
V
CC5 is the 5 V logic supply for the Dual Firing Airbag IC.
2.1.2
Power Supply
V
Boost
Input pin
V
Boost is a supply voltage for the Dual Firing Airbag IC, that is generated by an
external boost power supply. This Voltage is used for the firing circuits (
V
FV12).
2.1.3
Supply Voltage for High Side Gates V
CHP
Input pin
V
CHP is the supply for the high side DMOS Gates of the squib drivers. If VCHP is
not externally connected
V
CHP is internally connected to VBoost by a diode. This means
that the high side switch has a higher voltage drop since the firing voltage is smaller than
V
CHP in the case that VFVxy = VBoost.
2.2
Serial Peripheral Interface (SPI) and Decoder Logic
The SPI of the Dual Firing Airbag IC is controlled by three input pins: CSN, DI and CLK.
The Chip Select Negative pin CSN allows the individual selection of different slave SPI
devices. Slave devices that are not selected do not interfere with SPI bus activities.
A slave device will be selected by a low signal on pin CSN.
The Data Input pin DI is used for the serial data from the
C, synchronously clocked by
the Clock input pin CLK.
All commands, no matter which function, consist of 16 bits, so the airbag IC consists of
a 16 bit input shift register, a 16 bit latch and a decoder logic block for the generation of
the SPI command signals.
To provide higher security and to suppress data transfer errors in the event that the clock
signal includes spikes or glitches, a counter for 16 clock cycles is provided. Only if 16
clock cycles have occurred, the rising edge of CSN causes an internal signal LE (Latch
Enable) to transfer the data from the shift register to the 16 bit latch. A logic block
decodes the 16 bit word of the latch to address the desired functional block.
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