參數(shù)資料
型號： TLE5012-E0742
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號調(diào)理
英文描述： POSITION SENSOR, PDSO8
封裝： GREEN, PLASTIC, DSO-8
文件頁數(shù)： 22/56頁
文件大?。?/td> 2614K
代理商： TLE5012-E0742
TLE5012
Specification
Target Data Sheet
29
V 0.41, 2009-02
Data Communication via SSC
Figure 19
SSC Bit Ordering (Read Example)
The data communication via SSC interface has the following characteristic:
The data transmission order is “Most Significant Bit (MSB) first”.
Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
The SSC Interface is word-aligned. All functions are activated after each transmitted word.
A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer
immediately. The CRC calculator is automatically reset.
After changing the data direction, a delay (twr_delay) has to be considered before continuing the data transfer.
This is necessary for internal register access.
Every access to the TLE5012 with the number of data (ND)
≥ 1 is performed with address auto-increment.
At an overflow at address 3FH the transfer continuous at address 00H.
With ND = 0 no auto-increment is done and a continuously readout of the same address can be realized.
Afterwards no Safety Word is send and the transfer ends with high condition on CSQ.
After every data transfer with ND
≥ 1 the 16 bit Safety Word will be appended by the selected TLE5012.
At a rising edge of CSQ without data transfer before (no SCK-pulse), the update-registers are updated with
according values.
After sending the Safety Word the transfer ends. To start another data transfer, the CSQ has to be deselected
once for tCSoff.
The SSC is default Push-Pull. The Push-Pull driver is only active, if the TLE5012 has to send data, otherwise
the Push-Pull is disabled for receiving data from the microcontroller.
Cyclic Redundancy Check (CRC)
This CRC is according to the J1850 Bus-Specification.
Every new transfer resets the CRC generation.
Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
Generator-Polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
The remainder of the fast CRC circuit is initial set to ’11111111B’.
Remainder is inverted before transmission.
Figure 20
Fast CRC Polynomial Division Circuit
SCK
DATA
8
11
10
9
MSB
14
13
12
CSQ
SSC Transfer
LSB
321
7
6
5
4
Command Word
Data Word (s)
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
LSB
1
RW
ADDR
LENGTH
LOCK
MSB
twr_delay
UPD
xor
X7
X6
X5
X4
X3
X2
xor
X0
xor
Input
Serial
CRC
output
&
TX_CRC
1111
1
X1
parallel
Remainder
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