參數(shù)資料
型號: TLE5012-E0742
廠商: INFINEON TECHNOLOGIES AG
元件分類: 模擬信號調(diào)理
英文描述: POSITION SENSOR, PDSO8
封裝: GREEN, PLASTIC, DSO-8
文件頁數(shù): 16/56頁
文件大?。?/td> 2614K
代理商: TLE5012-E0742
TLE5012
Specification
Target Data Sheet
23
V 0.41, 2009-02
3.4.6
Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input ’CLK’ must fulfill certain requirements which are
described in the following:
The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike filtered.
The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min).
The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically.
Figure 13
External CLK Timing Definition
Table 9
CLK Timing Specification
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Input Frequency
fCLK
3.8
4.0
4.2
MHz
CLK Duty Cycle1)2)
1) Minimum Duty Cycle Factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min)
2) Maximum Duty Cycle Factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)
CLKDUTY
30
50
70
%
CLK Rise Time
tCLKr
-
30
ns
from VL to VH
CLK Fall Time
tCLKf
-
30
ns
from VH to VL
Digital Clock
fDIG
22.8
24
25.2
MHz
Internal Oscillator Frequency
fCLK
3.8
4.0
4.2
MHz
tCLKh
tCLKl
tCLK
t
VL
VH
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