參數(shù)資料
型號(hào)： TLC320AD90C
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： Stereo Audio Codec(立體聲音頻編碼譯碼器)
中文描述： 立體聲音頻編解碼器（立體聲音頻編碼譯碼器）
文件頁(yè)數(shù)： 28/51頁(yè)
文件大?。?/td> 219K
代理商： TLC320AD90C
2–14
2.3.7
The General Purpose register is used to control several miscellaneous functions of the TLC320AD90C:
microphone output select, microphone select, and loopback.
General Purpose Register (Index 20h)
This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
The default value of this register is 0000h. The General Purpose register definitions are listed in Table 2–12.
Table 2–12. General Purpose Register Definitions
BIT
FUNCTION
MIX
Mono select. 0 = Mix, 1 = Mic
MS
Mic select. 0 = MIC1, 1 = MIC2
LPBK
ADC/DAC loopback mode.
0: Off
1: Enables loopback of the ADC output to the DAC input without involving
the AC-Link thus allowing for full system performance measurements.
2.3.8
The Power-Down Control/Status register is a read/write register used to program power-down states and
monitor subsystem readiness. The lower half of this register is read-only status with a one indicating that
the subsection is ready. Ready is defined as the subsection is able to perform in its nominal state. When
this register is written, the bit values received on the AC-Link have no effect on read-only bits 0–7.
Power-Down Control/Status Register (Index 26h)
When the AC-Link Codec Ready indicator bit (SDATA_IN, slot 0, bit 15) is a one, the AC-Link and
TLC320AD90C control and status registers are in a fully operational state. The digital controller must further
probe this Power-Down Control/Status register to determine which subsections, if any, are ready. The
Power-Down Control/Status register bits D0–D3 definitions are listed in Table 2–13.
Table 2–13. Power-Down Control/Status Register Bits D0–D3 Definitions
BIT
FUNCTION
REF
Vref is up to nominal level
ANL
Analog mixers, etc. ready
DAC
DAC section ready
ADC
ADC section ready
The power-down modes include the following:
The first three bits (PR0–PR2) are to be used individually rather than in combination with each
other
The last bit, PR3 can be used with PR2 or by itself
PR0 and PR1 control the PCM ADCs and DACs only
The Power-Down Control/Status register bits D8–D13 definitions are listed in Table 2–14.
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