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參數(shù)資料
| 型號(hào)： | TLC320AD90C |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio Codec(立體聲音頻編碼譯碼器) |
| 中文描述： | 立體聲音頻編解碼器（立體聲音頻編碼譯碼器） |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 219K |
| 代理商： | TLC320AD90C |
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2–7
2.2.4
The TLC320AD90C implementation of the AC-Link can be placed in a low-power mode (see Section 2.7,
Power-Down Management). When the TLC320AD90C Power Down register (26h) is programmed to the
appropriate value, both BIT_CLK and SDATA_IN are brought to and held at low-voltage logic levels.
AC-Link Low-Power Mode
As shown in Figure 2–4, BIT_CLK and SDATA_IN are transmitted low immediately following the decode of
the write to the Power Down Register (26h) with PR4. When the digital controller driver is at the point where
it is ready to program the TLC320AD90C into its low-power mode, slots one and two are assumed to be the
only valid stream in the audio output frame. (At this point, all sources of audio input are assumed to have
also been neutralized.)
Slot 12
Prev. Frame
TAG
Write To
00
×
26
Data
PR4
Slot 12
Prev. Frame
TAG
SYNC
BIT_CLK
(Not To Scale)
SDATA_OUT
SDATA_IN
Figure 2–4. TLC320AD90C Power-Down Mode Timing
The digital controller must also drive SYNC and SDATA_OUT low after programming the TLC320AD90C
to this low-power halted mode.
Once the TLC320AD90C has been instructed to halt BIT_CLK, a special wake-up protocol must be used
to bring the AC-Link to the active mode since normal audio output and input frames cannot be communicated
in the absence of BIT_CLK.
The AC-Link can be made active again by means of a warm reset or a cold reset. See Section 2.5, Resetting
the TLC320AD90Cfor details on the procedure. In summary, a warm reset is accomplished by asserting
SYNC in the absence of BIT_CLK. The TLC320AD90C responds according to the protocol. A warm reset
retains the values programmed into the registers. A cold reset is accomplished by asserting RESET. Again,
the TLC320AD90C responds according to the protocol. A cold reset sets all register values to their default
values. Note that for both cases of a reset, the signals RESET and SYNC are treated as asynchronous
inputs.
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