- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384004 > TLC320AD75C (Texas Instruments, Inc.) 20-Bit Sigma-Delta Stereo ADA Circuit PDF資料下載
參數(shù)資料
| 型號： | TLC320AD75C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 20-Bit Sigma-Delta Stereo ADA Circuit |
| 中文描述： | 20位Σ-Δ立體聲電路反傾銷協(xié)定 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 211K |
| 代理商： | TLC320AD75C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
2–4
2.6
2.6.1
The master-clock circuit generates and distributes necessary clocks throughout the device. MCLKI is the
external master-clock input. The sample rate of the data paths is set as LRCKA = MCLKI/256. With a fixed
oversampling ratio of 64
×
f
s
, the effect of changing MCLKI is shown in Table 2–1.
Table 2–1. ADC Master Clock to Sample-Rate Comparison
Master Clock
Master-Clock Circuit for ADC
MCLKI
(MHz)
SCLKA
(MHz)
LRCKA
(kHz)
12.2880
3.0720
48
11.2896
2.8224
44.1
8.1920
2.0480
32
When the TLC320AD75C is in master mode (M_S is pulled high) SCLKA is derived from MCLKI in order
to provide clocking of the serial communications between the sigma-delta audio ADC and a digital signal
processor (DSP) or control logic. This is equivalent to a clock running at 64
×
LRCKA.
When the TLC320AD75C is in slave mode (M_S is connected to V
SS1
), SCLKA is externally derived. For
SCLKA use of a clock running at 64 times LRCKA is recommended.
2.6.2
The timing and control circuit generates and distributes necessary clocks throughout the TLC320AD75C.
XIN is the oscillator input terminal or can receive an external master-clock input. The sample rate of the data
paths is set as LRCKD = XIN/512. With a fixed oversampling ratio of 32
×
and each PWM output value
requiring 16 XIN cycles, the effect of changing XIN is shown in Table 2–2.
Master-Clock Circuit for DAC
Table 2–2. DAC Master Clock to Sample-Rate Comparison
XIN
(MHz)
256CK
(MHz)
LRCKD
(kHz)
24.5760
12.2880
48.0
22.5792
11.2896
44.1
16.3840
8.1920
32.0
The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
master-clock frequency. Some of the functions of the converter, such as the deemphasis filter, operate only
at the frequencies shown in Table 2–2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC320AD77C | 24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD80C | Audio Processor Subsystem |
| TLC320AD81CDBT | Stereo Audio Digital Equalizer DC |
| TLC320AD81C | Stereo Audio Digital Equalizer DC |
| TLC339CDB | LinCMOSE MICROPOWER QUAD COMPARATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD75CDL | 制造商:Texas Instruments 功能描述: |
| TLC320AD77 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec |
| TLC320AD77C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD77CDB | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD77CDBG4 | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。