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參數(shù)資料
| 型號： | TLC320AD75C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 20-Bit Sigma-Delta Stereo ADA Circuit |
| 中文描述： | 20位Σ-Δ立體聲電路反傾銷協(xié)定 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大?。?/td> | 211K |
| 代理商： | TLC320AD75C |
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1–5
1.6
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
ADOUT
12
O
20-bit ADC data output. ADOUT provides the MSB first in 2’s-complement data format
and is left justified within the 32-bit packet for each channel. The output level is 3.3 V
for V35A = 3.3 V (see Figure 2–6).
Analog power-down mode. APD disables the ADC analog modulators. The ADC
single-bit modulator outputs become invalid, rendering the outputs of the digital filters
invalid. When APD is pulled high, normal operation of the device is resumed.
APD
6
I
AVDD
AVSS
AVSSB
4
Analog power supply voltage for ADC modulators
5
Analog ground for ADC modulators
51
Analog substrate ground for ADC modulators
CDIN
19
I
Attenuation mode and system control mode input for DAC. CDIN is a 24-bit stream
with a 16-bit data word followed by an 8-bit device address. This stream is configured
with the MSB first (see Section 2.15, Sigma-Delta DAC Modulator).
DDATA
27
I
DAC input data in 2’s-complement data format. MSB/LSB first and 20-bit/16-bit input
formats are selectable by using the DAC control registers (see Section 2.15,
Sigma-Delta DAC Modulator).
DPD
16
I
Digital power-down mode. The DPD shuts down the ADC digital decimation filters and
clock generators, and provides a digital reset. All digital outputs of the ADC function,
are brought to unasserted states. When DPD is pulled high, normal operation of the
device is resumed. When in slave mode operation, after the rising edge of DPD, the
ADC system is synchronized.
INIT
18
I
Initial DAC reset signal. The DAC device is activated on the rising edge of INIT. When
INIT is brought low, the DAC is reset when LRCKD is present.
INLM
55
I
Inverting input for the left channel analog modulator
INLP
56
I
Noninverting input for the left channel analog modulator
INRM
2
I
Inverting input for the right channel analog modulator
INRP
1
I
Noninverting input for the right channel analog modulator
LATCH
21
I
Latch signal for the DAC control serial data. Attenuation/system-control data loads
into the internal registers when LATCH is brought low.
LRCKA
10
I/O
Left/right clock for ADC. LRCKA signifies whether the serial data is associated with
the left channel ADC (when LRCKA is high) or the right channel ADC (when LRCKA
is low). LRCKA is normally connected to LRCKD. LRCKA is output when configured
in master mode.
LRCKD
28
I
Left/right clock for DAC. LRCKD signifies whether the serial data is associated with
the left channel DAC (when LRCKD is high) or the right channel DAC (when LRCKD
is low). LRCKD is normally connected to LRCKA.
LVDD
52
Digital power supply for analog modulators. LVDD is normally connected to AVDD
through a 50-
resistor.
LVSS
53
Digital ground for analog modulators. LVSS is normally connected to AVSS through a
50-
resistor.
L1
41
O
Left channel DAC PWM output 1
L2
39
O
Left channel DAC PWM output 2
MCLKI
15
I
Master clock input for ADC. MCLKI operates at 256 times the sample rate (i.e. 256
times LRCKA). MCLKI is normally connected to 256CK through a 50-
resistor.
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| TLC320AD75CDL | 制造商:Texas Instruments 功能描述: |
| TLC320AD77 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec |
| TLC320AD77C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD77CDB | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD77CDBG4 | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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