參數(shù)資料
型號(hào): TLC320AD55C
廠商: Texas Instruments, Inc.
英文描述: Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口)
中文描述: sigma - delta模擬接口電路(Σ-Δ模擬接口)
文件頁(yè)數(shù): 17/41頁(yè)
文件大小: 256K
代理商: TLC320AD55C
2–5
2.2.5
This input provides for hardware programming requests for secondary communication. It works in
conjunction with the control bit D00 of the secondary data word. The signal on FC is latched 1/2 shift clock
after the rising edge of the next internally generated primary frame-sync interval. FC should be tied low when
not being used (see Section 3.2 Secondary Serial Communication).
Hardware Program Terminal (FC)
2.2.6
The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from
DOUT and into DIN begins on the falling edge of the frame-sync signal.
Frame-Sync
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
the 16-bit data transfer.
2.2.7
The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta
modulator. The performance of the AUX channel is similar to the normal input channel.
Multiplexed Analog Input
2.2.8
The signal applied to the terminals INM and INP should be differential to preserve the device specifications
(see Figure 2–3). A single-ended input signal should always be converted to a differential input signal prior
to being used by the TLC320AD55C. The signal source driving the analog inputs (INM, INP, AUXM, AUXP)
should have a low source-impedance for lowest noise performance and accuracy.
Analog Input
4 V
2.5 V
1 V
4 V
2.5 V
1 V
INP
INM
TLC320AD55C
Figure 2–3. Differential Analog Input Configuration
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TLC320AD56 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Analog Interface Circuit
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