- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384004 > TLC320AD55C (Texas Instruments, Inc.) Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) PDF資料下載
參數(shù)資料
| 型號： | TLC320AD55C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| 中文描述： | sigma - delta模擬接口電路（Σ-Δ模擬接口） |
| 文件頁數(shù)： | 16/41頁 |
| 文件大?。?/td> | 256K |
| 代理商： | TLC320AD55C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
2–4
2.2.1.3
Software and Hardware Power-Down
Given the definitions above, the software-programmed power-down condition is cleared by programming
the software bit (control 1 register bit 6) to a 0 or is cleared by cycling the power to the device, bringing
PWRDWN low, or bringing RESET low (see Figure 2–2).
PWRDWN removes power to the entire chip. The software-programmable, power-down bit only removes
power from the analog section of the chip, which allows a software power-up function. Cycling the
power-down terminal from high to low and back to high resets all flip-flops and latches that are not externally
programmed, thereby preserving the register contents with the exception that the software power-down bit
is cleared.
When PWRDWN is not being used, it should be tied high [V
DD
(ADC) is preferred].
Digital Circuitry
Power-Down
PWRDWN
Bit 6 is Programmed
Through a Secondary
Write Operation
Analog Circuitry
Power-Down
Clear
(For Control
Register 1,
Bit 6)
Internal TLC320AD55C
Figure 2–2. Internal Power-Down Logic
2.2.2
Master Clock Circuit
The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK [SCLK = MCLK/(Fsclk
×
2), Fsclk = 1,2,3,...,256] in order
to provide clocking of the serial communications between the device and a digital signal processor (DSP).
The sample rate of the data paths is set as MCLK/(Fk
×
256). Fk and Fsclk are programmable register values
used as divisors of MCLK. The default value for the Fk and Fsclk register is 8 (decimal).
2.2.3
Data Out (DOUT)
DOUT is taken from the high-impedance state by the falling edge of the frame-sync signal. The most
significant data bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK (internal or external) after
the falling edge of the frame-sync signal. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to zero (see the serial communications section). When a
register read is not requested, the secondary word is all zeroes.
2.2.4
Data In (DIN)
In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 3 Serial Communications).
相關PDF資料 |
PDF描述 |
|---|---|
| TLC320AD56(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口) |
| TLC320AD56C | Sigma-Delta Analog Interface Circuit |
| tlc320ad56c | Sigma-Delta Analog Interface Circuit(Sigma-Delta 模擬接口電路) |
| TLC320AD57(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC) |
| TLC320AD57C | Sigma-Delta Stereo Analog-to-Digital Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD56 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Analog Interface Circuit |
| TLC320AD56C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Analog Interface Circuit |
| TLC320AD56CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC320AD56CPT | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC320AD57 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復。