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參數(shù)資料
| 型號： | TH50VSF3583AASB |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝多芯片集成電路硅柵CMOS |
| 文件頁數(shù)： | 15/50頁 |
| 文件大?。?/td> | 548K |
| 代理商： | TH50VSF3583AASB |
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TH50VSF3582/3583AASB
2001-06-08 15/50
DC CHARACTERISTICS
(Ta
=
-30°~85°C, V
CCs
/V
CCf
=
2.67 V~3.3 V)
SYMBOL
PARAMETER
CONDITION
MIN
TYP. MAX UNIT
I
IL
Input Leakage Current
V
IN
=
0 V~V
CC
±
1
μ
A
I
ILW
Input Leakage Current
(
/ACC
WP
pin)
0 V
≤
V
IN
≤
V
CC
±
10
μ
A
I
SOH
SRAM Output High Current
V
OH
=
V
CCs
0.5 V
0.5
mA
I
SOL
SRAM Output Low Current
V
OL
=
0.4 V
2.1
mA
I
FOH1
Flash Output High Current (TTL) V
OH
=
2.4 V
0.4
mA
V
OH
=
V
CCf
×
0.85
2.5
mA
I
FOH2
Flash Output High Current
(CMOS)
V
OH
=
V
CCf
0.4 V
100
μ
A
I
FOL
Flash Output Low Current
V
OL
=
0.4 V
4
mA
I
LO
Output Leakage Current
V
OUT
=
0 V~V
CC
,
OE
=
V
IH
±
1
μ
A
I
CCO1
Flash Average Read Current
CEF
=
V
IL
,
OE
=
V
IH
, I
OUT
=
0 mA,
t
cycle
=
t
RC
(min)
30
mA
I
CCO2
Flash Average Program/
Erase Current
CEF
=
V
IL
,
OE
=
V
IH
, I
OUT
=
0 mA
15
mA
t
cycle
=
t
RC
50
I
CCO3
S
1
CE
OE
=
V
IH
, I
OUT
=
0 mA
=
V
IL
, CE2S
=
V
IH
,
t
cycle
=
1 MHz
10
mA
t
cycle
=
t
RC
45
I
CCO4
SRAM Average Operating
Current
S
1
CE
CE2S
=
V
CCs
0.2 V, I
OUT
=
0 mA
=
0.2 V,
OE
=
V
CCs
0.2 V,
t
cycle
=
1 MHz
5
mA
I
CCO5
Flash Average
Read-While-Program Current
V
IN
=
V
IH
/V
IL
, I
OUT
=
0 mA, t
cycle
=
t
RC
(min)
45
mA
I
CCO6
Flash Average
Read-While- Erase Current
V
IN
=
V
IH
/V
IL
, I
OUT
=
0 mA, t
cycle
=
t
RC
(min)
45
mA
I
CCO7
Flash Average Program-While-
Erase-Suspend Current
V
IN
=
V
IH
/V
IL
, I
OUT
=
0 mA
15
mA
I
CCS1
Flash Standby Current
CEF
=
RESET
=
V
CCf
or
RESET
=
V
SS
10
μ
A
I
CCS2
Flash Standby Current
(Automatic Sleep Mode
(1)
)
V
IH
=
V
CCf
or V
IL
=
V
SS
10
μ
A
I
CCS3
S
1
CE
=
V
IH
or CE2S
=
V
IL
2
mA
Ta
=
25°C
1
V
CCs
=
3.3 V
Ta
=
30~85°C
10
Ta
=
25°C
0.01
0.5
Ta
=
30~40°C
1
I
CCS4
SRAM Standby Current
S
1
CE
or CE2S
=
0.2 V
(2)
=
V
CCs
0.2 V
V
CCs
=
3.0 V
Ta
=
30~85°C
5
μ
A
I
ACC
High Voltage Input Current for
/ACC
WP
8.5 V
≤
V
ACC
≤
9.5 V
20
mA
(1) The device is going to Automatic Sleep Mode, when address remain steady during 150 ns.
(2) In Standby Mode, with
S
1
CE
≥
V
CCs
0.2 V, these limits are guaranteed when CE2S
≥
V
CCs
0.2 V or CE2S
≤
0.2 V and
CIOS
≥
V
CCs
0.2 V or CIOS
≤
0.2 V.
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