參數(shù)資料
型號(hào)： TEA1208T
廠商： NXP SEMICONDUCTORS
元件分類： 穩(wěn)壓器
英文描述： High efficiency DC/DC converter
中文描述： SWITCHING REGULATOR, 330 kHz SWITCHING FREQ-MAX, PDSO8
封裝： 3.90 MM, PLASTIC, MS-012, SOT96-1, SO-8
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 88K
代理商： TEA1208T
2002 Nov 15
5
Philips Semiconductors
Product specification
High efficiency DC/DC converter
TEA1208T
PINNING
SYMBOL
PIN
DESCRIPTION
U/D
1
up-or-down conversion
selection input; active LOW for
up conversion
current limiting resistor
connection
output voltage in up conversion;
input voltage in down
conversion
inductor connection
synchronization clock input
ground
feedback input
shut-down input
ILIM
2
UPOUT/DNIN
3
LX
SYNC
GND
FB
SHDWN
4
5
6
7
8
handbook, halfpage
MCE154
1
2
3
4
8
7
6
5
U/D
SHDWN
ILIM
FB
UPOUT/DNIN
GND
LX
SYNC
TEA1208T
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1208T DC/DC converter is able to operate in
either PFM (discontinuous conduction) or PWM
(continuous conduction) mode. All switching actions are
completely determined by a digital control circuit which
uses the output voltage level as its control input. This
special design enables the use of a pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete operating range of the
converter.
When high output power is requested, the device operates
in PWM (continuous conduction) mode. This results in
minimum AC currents in the circuit components and hence
optimum efficiency, minimum costs and low EMC. In PWM
mode, the output voltage is allowed to vary between a
window represented by two predefined voltage levels.
As long as the output voltage stays within this window,
switching continues in a fixed pattern. When the output
voltage reaches a window border, the digital controller
immediately adjusts the pulse width and inserts a current
stepsothattheoutputvoltagestayswithinthewindowwith
higher or lower current capability. This approach enables
very fast reaction to load variations. Figure 3 shows the
converter’s response to a sudden load increase. The
upper trace shows the output voltage. The ripple on top of
the DC level is a result of the current in the output
capacitor, which changes sign twice per cycle, times the
capacitor’s internal Equivalent Series Resistance (ESR).
Aftereachramp-downoftheinductorcurrent,i.e.whenthe
ESR effect increases the output voltage, the converter
determines what to do in the next cycle.
As soon as more load current is taken from the output the
output voltage starts to decay.
When the output voltage becomes lower than the low limit
of the window, it is corrected by extending the period of the
inductor current ramp-up time. As a result, the DC current
level is increased and normal PWM control can continue.
The output voltage (including ESR effect) is again within
the predefined window. Figure 4 depicts the spread of the
output voltage window. The absolute value is most
dependent on spread, while the actual window size is not
affected. For a given device, the output voltage will not
vary more than 2% typically.
In low output power situations, the TEA1208T will switch
over to PFM (discontinuous conduction) operating mode.
In this mode, regulation information obtained in previous
PWM operating modes is used. This results in optimum
inductor peak current levels in the PFM mode, which are
slightly larger than the inductor ripple current in the PWM
mode. As a result, the transition between PFM and PWM
mode is optimum under all circumstances. In the PFM
mode the TEA1208T regulates the output voltage to the
high window limit as shown in Fig.3.
Synchronous rectification
For optimum efficiency over the whole load range,
synchronous rectifiers inside the TEA1208T ensure that
during the whole second switching phase, all inductor
current will flow through the low-ohmic power MOSFETs.
Special circuitry is included which detects that the inductor
current reaches zero. Following this detection, the digital
controller switches off the power MOSFET and starts
regulation.
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