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參數(shù)資料
| 型號： | TE28F800C3TD70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP-48 |
| 文件頁數(shù)： | 71/72頁 |
| 文件大小： | 1083K |
| 代理商： | TE28F800C3TD70 |
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Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
8
Order Number: 290645, Revision: 023
2.0
Functional Overview
This section provides an overview of the Intel
Advanced+ Boot Block Flash Memory (C3) device
features and architecture.
2.1
Product Overview
The C3 flash memory device provides high-performance asynchronous reads in package-
compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally
sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at
either the top or bottom of the device’s memory map. The rest of the memory array is grouped into
32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3 V) and erase
and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC and VPP can be tied
together for a simple, ultra-low-power design. In addition to I/O voltage flexibility, the dedicated
VPP input provides complete data protection when VPP ≤ VPPLK.
The Intel Advanced+ Boot Block Flash Memory (C3) device features a 128-bit protection
register enabling security techniques and data protection schemes through a combination of
factory-programmed and user-programmable OTP data registers. Zero-latency locking/unlocking
on any memory block provides instant and complete protection for critical system code and data.
Additional block lock-down capability provides hardware protection where software commands
alone cannot change the block’s protection status.
A command User Interface (CUI) serves as the interface between the system processor and internal
operation of the device. A valid command sequence issued to the CUI initiates device automation.
An internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS), standby
mode, and deep power-down mode. The device automatically enters APS mode following read
cycle completion. Standby mode begins when the system deselects the flash memory by
deasserting Chip Enable, CE#. The deep power-down mode begins when Reset Deep Power-
Down, RP# is asserted, which deselects the memory and places the outputs in a high-impedance
state, producing ultra-low power savings. Combined, these three power-savings features
significantly enhanced power consumption flexibility.
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| TE28F800CEB120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8-MBIT (512K X 16, 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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