參數(shù)資料
型號(hào)： TE28F800C3TD70
廠(chǎng)商： INTEL CORP
元件分類(lèi)： PROM
英文描述： 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, TSOP-48
文件頁(yè)數(shù)： 35/72頁(yè)
文件大?。?/td> 1083K
代理商： TE28F800C3TD70
Intel Advanced+ Boot Block Flash Memory (C3)
May 2005
Intel Advanced+ Boot Block Flash Memory (C3)
Datasheet
40
Order Number: 290645, Revision: 023
9.1.4
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
9.1.5
Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-
impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required
until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from
reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.
The CUI resets to read-array mode, the Status Register is set to 0x80, and all blocks are locked. See
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be
aborted; the memory contents at the aborted location (for a program) or block (for an erase) are no
longer valid, since the data may be partially erased or written. The abort process goes through the
following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes
time tPLRH to complete.
2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH)
or enter reset mode (if RP# is deasserted after tPLRH). See Figure 13, “Reset Operations
In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL
must be observed before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when
RP# goes high.
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor reads from the flash memory. Automated flash memories provide
status information when read during Program or Block-Erase operations. If a CPU reset occurs
with no flash memory reset, proper CPU initialization may not occur because the flash memory
may be providing status information instead of array data. Intel flash memories allow proper CPU
initialization following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
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