參數(shù)資料
型號(hào): TDA9884TS
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: I2C-bus controlled multistandard alignment-free IF-PLL for mobile reception
中文描述: AM/FM, AUDIO/VIDEO DEMODULATOR, PDSO24
封裝: 5.30 MM, PLASTIC, SOT-340-1, MO-150, SSOP-24
文件頁(yè)數(shù): 14/55頁(yè)
文件大小: 231K
代理商: TDA9884TS
2003 Nov 28
14
Philips Semiconductors
Product specification
I
2
C-bus controlled multistandard alignment-free
IF-PLL for mobile reception
TDA9884TS
8.1.1
S
LAVE ADDRESS
The first module address MAD1 is the standard address (see Table 1).
Table 4
Slave addresses; notes 1 and 2
Notes
1.
2.
For MAD activation via external resistor: see Table 1 and Fig.21.
For applications without I
2
C-bus: see Tables 18 and 19.
8.1.2
D
ATA BYTE
Table 5
Data read register (status register)
Table 6
Description of status register bits
Note
1.
If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for
fast lock-in behaviour.
SLAVE ADDRESS
BIT
NAME
VALUE
(HEX)
A6
A5
A4
A3
A2
A1
A0
MAD1
MAD2
MAD3
MAD4
43
42
4B
4A
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
AFCWIN
VIFLEV
CARRDET
AFC4
AFC3
AFC2
AFC1
PONR
BIT
VALUE
DESCRIPTION
AFCWIN
AFC window
VCO in
±
1.6 MHz AFC window; note 1
VCO out of
±
1.6 MHz AFC window
VIF input level
high level; VIF input voltage
200
μ
V (typically)
low level
FM carrier detection
detection
no detection
Automatic frequency control
see Table 7
Power-on reset
after Power-on reset or after supply breakdown
after a successful reading of the status register
1
0
VIFLEV
1
0
CARRDET
1
0
AFC[4:1]
PONR
1
0
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