參數(shù)資料
型號(hào)： TDA9615H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Audio processor for VHS hi-fi(應(yīng)用于VHS高保真的音頻處理器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 9/44頁(yè)
文件大?。?/td> 263K
代理商： TDA9615H
1997 Jun 16
9
Philips Semiconductors
Preliminary specification
Audio processor for VHS hi-fi
TDA9615H
I
2
C-BUS PROTOCOL
Addressing and data bytes
For programming the device (write mode) seven data byte registers are available; they are addressable via eight
subaddresses. Automatic subaddress incrementing enables the writing of successive data bytes in one transmission.
During power-on, data byte registers are reset to a default state by use of a Power On Reset (POR) circuit which signal
is derived from the internally generated I
2
C-bus supply voltage (V5OUT; pin 38). For reading from the device (read mode)
one data byte register is available without subaddressing.
Table 1
TDA9615H addresses and data bytes
Notes
1.
Use of subaddress F0H to F7H (1111 0XXX) instead of 00H to 07H (0000 0XXX) disables the automatic subaddress
incrementing allowing continuous writing to a single data byte register.
The state of unused read bits are not reliable; their state may change during development.
2.
Table 2
Status of data bytes after POR
Note
1.
For eventual future compatibility it is advised to keep unused write bits equal to POR state.
DATA BYTE
ADDRESS
Write mode
Slave address byte (B8H)
Subaddress bytes (00H to 07H)
Control byte (subaddress 00)
Select byte (subaddress 01)
Input byte (subaddress 02)
Output byte (subaddress 03)
Left volume byte
(subaddress 04)
Right volume byte
(subaddress 05)
Volume byte (subaddress 06)
Power byte (subaddress 07)
1
0
(1)
AFM
DOS1
i7
LOH
I7
0
0
(1)
DOC
DOS0
IS2
OSN
VLS
1
0
(1)
SHH
s5
IS1
OSR
VL5
1
0
(1)
DETH
s4
IS0
OSL
VL4
1
0
NTSC
NIL3
NS2
EOS
VL3
0
0 or 1
MUTE
NIL2
NS1
LOS
VL2
0
0 or 1
STBP
NIL1
NS0
DOS
VL1
0
0 or 1
STBA
NIL0
i0
RFCM
VL0
r7
VRS
VR5
VR4
VR3
VR2
VR1
VR0
simultaneous loading of subaddress 04 and subaddress 05 register
CALS
VCCH
TEST
PORR
p3
p2
p1
p0
Read mode
Slave address byte (B9H)
Read byte
1
CALR
0
AUTN
1
0
(2)
1
POR
1
0
(2)
0
1
(2)
0
0
(2)
1
0
(2)
DATA BYTE
ADDRESS
Control byte
Select byte
Input byte
Output byte
Left volume byte
Right volume byte
Power byte
1
0
0
(1)
0
0
(1)
0
(1)
0
0
0
0
0
1
1
0
0
1
(1)
0
0
0
0
0
0
1
(1)
0
0
0
0
0
1
0
1
0
0
0
0
(1)
1
0
1
0
0
0
0
(1)
0
0
1
0
0
0
0
(1)
0
0
0
(1)
1
0
0
0
(1)
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