參數(shù)資料
型號: TDA9605H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Audio processor with head amplifier for VHS hi-fi
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
文件頁數(shù): 18/52頁
文件大?。?/td> 244K
代理商: TDA9605H
1999 Apr 14
18
Philips Semiconductors
Product specification
Audio processor with head amplifier for VHS hi-fi
TDA9605H
7
I
2
C-BUS PROTOCOL
7.1
Addresses and data bytes
Full control of the TDA9605H is accomplished via the 2-wire I
2
C-bus. Bus speeds up to 400 kbits/s can be used in
accordance with the I
2
C-bus fast-mode specification.
Seven data byte registers are available for programming the device (write mode) and one data byte register is available
for reading data from the device (read mode). The registers are addressable via eight subaddresses. Automatic
subaddress incrementing enables writing of successive data bytes in one transmission.
During power-up, the data byte registers and auto-calibration registers are reset to a default state by the use of a
Power-On Reset (POR) circuit. The reset signal is derived from an internally generated voltage supplied by V
CC
.
Table 6
Addresses and POR state bits
Notes
1.
Continuous writing to a single data byte register is possible when subaddresses F0H to F7H (1111 0xxx) are used
instead of 00H to 07H (0000 0xxx). In that case automatic subaddress incrementing is disabled.
It is advised to keep the not-used write bits equal to the POR state to accommodate future compatibility.
You cannot rely upon the state of the not-used read bits because their state may change during development.
2.
3.
NAME
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write mode
Slave byte
Subaddress byte
B8H
00H to 07H;
note 1
subaddress 00H AFM
1
0
0
0
1
0
1
0
1
0
0
0 or 1
0
0 or 1
0
0 or 1
Control byte
POR state
Select byte
POR state
Input byte
POR state
Output byte
POR state
Left volume byte
POR state
Right volume byte
POR state
Volume byte
Power byte
POR state
DOC
0
DOS0
0
IS2
0
OSN
0
VLS
1
VRS
1
SHH
0
s5
0
(2)
IS1
0
OSR
0
VL5
0
VR5
0
DETH
0
HRL
0
IS0
0
OSL
0
VL4
0
VR4
0
NTSC
1
NIL3
0
NS2
1
EOS
0
VL3
0
VR3
0
HAC2
0
NIL2
0
NS1
1
LOS
0
VL2
0
VR2
0
HAC1
0
NIL1
0
NS0
1
DOS
0
VL1
0
VR1
0
HAC0
0
NIL0
0
i0
0
(2)
RFCM
1
VL0
0
VR0
0
1
subaddress 01H DOS1
0
subaddress 02H i7
0
(2)
subaddress 03H LOH
0
subaddress 04H l7
0
(2)
subaddress 05H r7
0
(2)
subaddress 06H simultaneous loading of the subaddress 04H and subaddress 05H registers
subaddress 07H CALS
VCCS
TEST
0
0
0
PORR
0
HPD
0
MUTE
1
STBP
0
STBA
0
Read mode
Slave address byte
Read byte
B9H
B9H
1
CALR
0
AUTN
1
CALE
1
POR
1
0
(3)
0
0
(3)
0
0
(3)
1
0
(3)
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