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參數(shù)資料
| 型號(hào)： | TDA9112A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HIGH-END I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 高端的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁數(shù)： | 48/60頁 |
| 文件大?。?/td> | 781K |
| 代理商： | TDA9112A |
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TDA9112A
48/60
Figure 17. Shape characteristic versus
HVDC-HSHAP
register adjustment.
9.7 DC/DC controller section
The section is designed to control a switch-mode
DC/DC converter. A switch-mode DC/DC conver-
tor generates a DC voltage from a DC voltage of
different value (higher or lower) with little power
losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize poten-
tial interference into the picture.
Its operation is similar to that of standard UC3842.
The schematic diagram of the DC/DC controller is
in
Figure 18
. The
BOut
output controls an external
switching circuit (a MOS transistor) delivering
pulses synchronized on horizontal deflection fre-
quency, the phase of which depends on H/W and
I2C-bus configuration. See the table at the end of
this chapter. Their duration depends on the feed-
back provided to the circuit, generally a copy of
DC/DC converter output voltage and a copy of cur-
rent passing through the DC/DC converter circuitry
(e.g. current through external power component).
The polarity of the output can be controlled by
BOutPol
I2C-bus bit. A NPN transistor open-collec-
tor is routed out to the
BOut
pin.
During the operation, a sawtooth is to be found on
pin
BISense
, generated externally by the applica-
tion. According to
BOutPh
I2C-bus bit, the R-S flip-
flop is set either at H-drive signal edge (rising or
falling, depending on
BOHEdge
I2C-bus bit), or a
certain delay (
tBTrigDel
) after middle of H-flyback,
or at horizontal frequency divided by two (phase
corresponding to
VHOThrHi
on the VCO ramp). The
output is set On at the end of the short pulse gen-
erated by the monostable trigger.
Timing of reset of the R-S flip-flop affects duty cy-
cle of the output square signal and so the energy
transferred from DC/DC converter input to its out-
put. A reset edge is provided by comparator C2 if
the voltage on pin
BISense
exceeds the internal
threshold
VThrBIsCurr
. This represents current lim-
itation if a voltage proportional to the current
through the power component or deflection stage
is available on pin
BISense
. This threshold is affect-
ed by voltage on pin
HPosF
, which rises at soft
start and descends at soft stop. This ensures self-
contained soft control of duty cycle of the output
signal on pin
BOut
. Refer to
Figure 10
. Another con-
dition for reset of the R-S flip-flop, OR-ed with the
one described before, is that the voltage on pin
BI-
Sense
exceeds the voltage V
C2
, which depends on
the voltage applied on input
BRegIn
of the error
amplifier O1. The two voltages are compared, and
the reset signal generated by the comparator C1.
The error amplifier amplifies (with a factor defined
by external components) the difference between
the input voltage proportional to DC/DC convertor
output voltage and internal reference
VBReg
. The
0
31
63
95
127
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
(
SHVDC-
HSHAP
)
HVDC-HSHAP
I2C register value
Power factor
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