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參數(shù)資料
| 型號(hào)： | TDA9112A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HIGH-END I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 高端的I2C可控?fù)隙榷嗤斤@示器處理器 |
| 文件頁數(shù)： | 16/60頁 |
| 文件大小： | 781K |
| 代理商： | TDA9112A |
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TDA9112A
16/60
Notes about EW drive section
Note 24:
KEYST
at medium (neutral) value.
Note 25:
TCC
at medium (neutral) value.
Note 26:
BCC
at medium (neutral) value.
Note 27:
PCC
at minimum value.
Note 28:
VPOS
at medium (neutral) value.
Note 29:
HSIZE
I2C field at maximum value.
Note 30:
VEW-DC
is defined as voltage at t
VR
=1/2 T
VR
.
Note 31:
Defined as difference of (voltage at t
VR
=0) minus (voltage at t
VR
=1/2 T
VR
).
Note 32:
Defined as difference of (voltage at t
VR
=T
VR
) minus (voltage at t
VR
=1/2 T
VR
).
Note 33:
VSIZE
at maximum value.
Note 34:
Difference (voltage at t
VR
=0) minus (voltage at t
VR
=T
VR
).
Note 35:
Ratio "A/B"of parabola component voltage at t
VR
=0 versus parabola component voltage at t
VR
=T
VR
.
See
Figure 2
.
Note 36:
VHEHT
>
VRefO
,
VVEHT
>
VRefO
Note 37:
V
EW-AC
is defined as overall peak-to-peak value between t
VR
=0 and t
VR
=T
VR
of all components other than
VEW-DC
(contribution of PCC, keystone correction, corner corrections and S- and W-corrections).
Note 38:
More precisely tracking with voltage on
HPLL1F
pin which itself depends on frequency at a rate given by
external components on PLL1 pins
Note 39:
VEW-DC[span]
=
VEW-DC
[
VHO
>
VHOThrfr
]
-
VEW-DC
[
HSIZE
=0000000b].
V
EW-AC
[f
max
]
=
V
EW-AC
[
VHO
>
VHOThrfr
].
Note 40:
Defined as difference of (voltage at t
VR
=1/4 T
VR
) minus (voltage at t
VR
=3/4 T
VR
).
Note 41:
Defined as difference of (voltage at t
VR
=1/2 T
VR
) minus (voltage at t
VR
=1/4 T
VR
).
Note 42:
EWSC
at medium (neutral) value.
Note 43:
EWWC
at medium (neutral) value.
Note 44:
Informative, not tested on each unit.
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