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參數(shù)資料
| 型號： | TDA9112 |
| 廠商： | 意法半導體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費用的I2C可控撓度多同步顯示器處理器 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 621K |
| 代理商： | TDA9112 |
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TDA9112
26/51
Sad17/D2 - HBOutEn
H
orizontal and
B
+
Out
put
En
able
0: Disabled, levels corresponding to “power
transistor off”on HOut and BOut pins(high
for HOut, high or low for BOut, depending
on
BOutPol
bit).
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is notinhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in ex-
ternal sawtooth configuration.
Sad17/D3 - BOHEdge
Selection of
Edge
of
H
orizontal drive signal to
phase
B
+ drive
O
utput signal on BOut pin. Only
applies if DC/DC convertor is in external saw-
tooth configuration and the bit
BOutPh
is set to 1,
otherwise
BOHEdge
has no effect.
0: Falling edge
1: Rising edge
Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV
Test bits. They must be kept at 0 level by appli-
cation S/W.
Read-out flags
SadXX/D0 - VDet
(
53
)
Flag indicating
Det
ection of
V
synchronization
pulses on VSyn pin.
0: Not detected
1: Detected
SadXX/D1 - HVDet
(
53
)
Flag indicating
Det
ection of
H
or H
V
synchroni-
zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
Note 53:
This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I
2
C Bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.
SadXX/D2 - VExtrDet
(
53
)
Flag indicating
Det
ection of
Extr
acted
V
ertical
synchronization signal from composite H+V sig-
nal applied on H/HVSyn pin
0: Not detected
1: Detected
SadXX/D3 - VPol
Flag indicating
Pol
arity of
V
synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal
0: Positive
1: Negative
SadXX/D4 - HVPol
Flag indicating
Pol
arity of
H
or H
V
synchroniza-
tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal
0: Positive
1: Negative
SadXX/D5 - XRayAlarm
Alarm
indicating that an event of excessive volt-
age has passed on XRay pin. Can only be reset
to 0 through I
2
C Busbit XRayResetor by power-
on reset.
0: No excess since last reset of the bit
1: At least one event of excess appeared
since thelast resetof thebit, HOut inhibited
SadXX/D6 - VLock
Status of“
Lock
ing” orstabilizing of
V
ertical oscil-
lator amplitude to an internal reference by AGC
regulation loop.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 - HLock
Status of
Loc
king of
H
orizontal PLL1
0: Locked
1: Not locked
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