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參數(shù)資料
| 型號： | TDA9112 |
| 廠商： | 意法半導體 |
| 英文描述： | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR |
| 中文描述： | 低費用的I2C可控撓度多同步顯示器處理器 |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 621K |
| 代理商： | TDA9112 |
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TDA9112
25/51
Sad06/D7 - BOutPol
Pol
arity of B+ drive signal on BOut pin
0: adapted to N type of power MOS - high
level to make it conductive
1: adaptedto Ptype ofpower MOS -low level
to make it conductive
Sad07/D7 - BOutPh
Ph
ase of start of B+ drive signal on BOut pin,
while in external sawtooth configuration
0: Just after horizontal flyback pulse
1: With one of edges of line drive signal on
HOut pin, selected by
BOHEdge
bit
Sad08/D7 - EWTrHFr
Tr
acking of all corrections contained in wave-
form on pin EWOut with
H
orizontal
Fr
equency
0: Not active
1: Active
Sad15/D7 - VDyCorPol
Pol
arity of
V
ertical
Dy
namic
Cor
rection wave-
form (parabola)
0: Concave(minimum in the middle of the pa-
rabola)
1: Convex (maximum in the middle of the pa-
rabola)
Sad16/D0 - HLockEn
Enable of output of
H
orizontal PLL1
Lock
/unlock
status signal on pin HLckVBk
0: Disabled, vertical blanking only on the pin
HLckVBk
1: Enabled
Sad16/D1 - PLL1InhEn
En
able of
Inh
ibition of horizontal
PLL1
during
extracted vertical synchronization pulse
0: Disabled, PLL1 is never inhibited
1: Enabled
Sad16/D2 - PLL1Pump
Horizontal
PLL1
charge
Pump
current
0: Slow PLL1, low current
1: Fast PLL1, high current
Sad16/D4 - SDetReset
Reset
to 0 of
S
ynchronization
Det
ection flags
VDet
,
HVDet
and
VExtrDet
of status register effect-
ed with ACK bit of I
2
C Bus data transfer into reg-
ister containing the
SDetReset
bit. Also see de-
scription of the flags.
0: No effect
1: Reset with automatic return of the bit to 0
Sad16/D5 - VSyncSel
V
ertical
Sync
hronization input
Sel
ection be-
tween the one extracted from composite HV sig-
nal on pin H/HVSyn and the one on pin VSyn.
No effect if
VSyncAuto
bit is at 1.
0: V.sync extractedfromcompositesignalon
H/HVSyn pin selected
1: V. sync applied on VSyn pin selected
Sad16/D6 - VSyncAuto
V
ertical
Sync
hronization input selection
Auto-
matic mode. If enabled, the device automatically
selects between the vertical sync extracted from
composite HV signal on pin H/HVSyn and the
one on pin VSyn, based on detection mecha-
nism. If both are present, the one coming first is
kept.
0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit
VSyncSel
has no effect
Sad16/D7 - XRayReset
Reset
to 0 of
XRay
flag of status register effect-
ed with ACK bit of I
2
C Bus data transfer into reg-
ister containing the
XRayReset
bit. Also see de-
scription of the flag.
0: No effect
1: Reset with automatic return of the bit to 0
Sad17/D0 - BlankMode
Blank
ing operation
Mode
0: Blanking pulse starting with detection of
vertical synchronization pulse and ending
with end of vertical oscillator discharge
(start ofvertical sawtoothramp onthe VOut
pin)
1: Permanentblanking - highblanking level in
composite signal on pin HLckVBk is per-
manent
Sad17/D1 - VOutEn
V
ertical
Out
put
En
able
0: Disabled,
V
offVOut
on VOut pin (see 6.5 -
Vertical section)
1: Enabled,verticalrampwith vertical position
offset on VOut pin
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