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參數(shù)資料
| 型號： | TDA8939 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Zero dead time Class-D 7.5 A power comparator |
| 中文描述： | 零死時間D類7.5甲功率比較 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 99K |
| 代理商： | TDA8939 |
9397 750 13023
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 01 — 22 April 2004
6 of 21
Philips Semiconductors
TDA8939
Zero dead time Class-D 7.5 A power comparator
The block diagram of diagnostic output including OTP, OCP and OVP is illustrated in
Figure 3
. The diagnostic output (pin 7) is an open-drain output; a pull-up resistor
connected to +V
pull-up
has to be applied externally.
8.3 Interfacing between controller and the TDA8939
For interfacing with a digital PWM controller IC or microcontroller in the final system
application the following inputs and outputs are available see
Table 4
and
5
.
8.3.1
Inputs
Fig 3.
OCP, OTP and OVP protection: S/R latch.
001aaa623
+
V
pull-up
OTP
LATCH
OCP
OVP
S
R
Q
enable
disable power stage
+
V
int
TDA8939
open-drain
DIAGN
CGND
R2
Rpu
C1
R1
Table 4:
Pin name
IN1P and
IN1N
IN2P and
IN2N
POWERUP
Inputs
Pin number
4 and 2
Description
full differential input for output channel 1; referenced with respect
to each other; common mode referenced to V
SSD
full differential input for output channel 2; referenced with respect
to each other; common mode referenced to V
SSD
standby switch; reference to CGND; at a LOW level the device is
in standby mode and consumes a very low standby current. At
HIGH level the device is DC-biased (switch-on of internal
reference voltages and currents). The device can only be
switched to full operating mode by the enable input, if the
power-up input is at HIGH level.
mode switch; reference to CGND; at a LOW level the power
D-MOS switches are open and the PWM output is floating; all
internal logic circuits are in reset condition. At a HIGH level the
power comparator is fully operational if the power-up input is also
at a HIGH level. In this condition the power comparator outputs
are controlled by the input pins (IN1P, IN1N, IN2P and IN2N); see
also
Figure 6
. The enable input signal is also used to reset the
protection latch.
9 and 11
5
ENABLE
6
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