參數(shù)資料
型號(hào)： TDA8757AHL/17
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： ADC
英文描述： 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝： PLASTIC, HLQFP-144
文件頁(yè)數(shù)： 9/37頁(yè)
文件大?。?/td> 908K
代理商： TDA8757AHL/17
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
17 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9.
I2C-bus and 3W-bus interfaces
9.1 Register denitions
The conguration of the registers is given in Table 4.
9.1.1
Subaddress
All the registers are dened by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I2C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
each register.
Bit Mode, used only with the I2C-bus, allows two modes for the programming:
Mode 0
Each register is programmed independently, by giving its subaddress
and its content.
Mode 1
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predened sequence of 16 bytes (from
subaddress 0000 to 1101).
The default values correspond to a VESA 1280
× 1024 at 75 Hz graphic mode.
9.1.2
Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in Table 5.
Table 4:
I2C-bus and 3W-bus registers
Function
name
Subaddress
Bit denition
Default
value
A7 A6 A5 A4 A3 A2 A1 A0 MSB
LSB
SUBADDR
X
Mode Sa3
Sa2
Sa1
Sa0
XXX1 0000
OFFSETR
XXXX
0000Or7
Or6
Or5
Or4
Or3
Or2
Or1
Or0
0111 1111
COARSER XXXX
0001Or8
Cr6
Cr5
Cr4
Cr3
Cr2
Cr1
Cr0
0010 0000
FINER
XXXX
0010X
Testvol Testvoh Fr4
Fr3
Fr2
Fr1
Fr0
X000 0000
OFFSETG
XXXX
0011Og7
Og6
Og5
Og4
Og3
Og2
Og1
Og0
0111 1111
COARSEG XXXX
0100Og8
Cg6
Cg5
Cg4
Cg3
Cg2
Cg1
Cg0
0010 0000
FINEG
XXXX
0101X
X
SlevelFg4
Fg3
Fg2
Fg1
Fg0
XX00 0000
OFFSETB
XXXX
0110Ob7
Ob6
Ob5
Ob4
Ob3
Ob2
Ob1
Ob0
0111 1111
COARSEB XXXX
0111Ob8
Cb6
Cb5
Cb4
Cb3
Cb2
Cb1
Cb0
0010 0000
FINEB
XXXX
1000X
X
Cken
Fb4
Fb3
Fb2
Fb1
Fb0
XX00 0000
CONTROL XXXX
1001Vlevel Hlevel
Edge
Up
Do
Ip2
Ip1
Ip0
0000 0111
VCO
XXXX
1010Z2
Z1
Z0
Vco1
Vco0
Di11
Di10
Di9
1011 1011
DIVIDER
(LSB)
XXXX
1011Di8
Di7
Di6
Di5
Di4
Di3
Di2
Di1
0100 1100
PHASE
XXXX
1100Di0
Ckrs
Ckext
P4
P3
P2
P1
P0
0000 0000
DEMUX
XXXX
1101Blk
Shpixel Ckrp
Ckdp Ckdd Shift
Odda Dmx
1000 0111
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