參數資料
型號: TDA8757AHL/17
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: PLASTIC, HLQFP-144
文件頁數: 14/37頁
文件大?。?/td> 908K
代理商: TDA8757AHL/17
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
21 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The default programmed value is as follows:
No external clock: bit ‘Ckext’ is logic 0
Phase shift for CKDATA is 0 deg.
9.1.8
DEMUX register
The default programming is:
Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1
First pixel not shifted: bit ‘Shpixel’ = 0
CKREFO with positive polarity: bit ‘Ckrp’ = 0
CKDATA not reversed: bit ‘Ckdp’ = 0
CKDATA not delayed: bit ‘Ckdd’ = 0
Interleaved outputs: bit ‘Shift’ = 1
Odd pixels on port A: bit ‘Odda’ = 1.
Demultiplexed outputs: bit ‘Dmx’ = 1
For timing diagrams concerning various settings of this register, see Figure 11 - 13.
9.1.9
Power-down mode
When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
When the device is in Power-down mode (pin PD = HIGH), the previously
programmed register values remain unaffected.
9.2 I2C-bus protocol
The address of the circuit for the I2C-bus is 1001 1XX0.
Bits ‘A1’ and ‘A0’ are xed by the potential on pins A2 and A1. Bit ‘RW’ must always
be equal to logic 0 because it is not possible to read the data in the register. The
timing and protocol for the I2C-bus are standard. Two sequences are available;
see Table 13 and 14.
Table 11: Phase registers bits
P4
P3
P2
P1
P0
Phase shift (deg)
000000
00001
11.25
...
11110
337.5
11111
348.75
Table 12: Register format
A6
A5
A4
A3
A2
A1
A0
RW
10011A2
A1
0
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