參數(shù)資料
型號: TDA8757AHL/17
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144
封裝: PLASTIC, HLQFP-144
文件頁數(shù): 11/37頁
文件大?。?/td> 908K
代理商: TDA8757AHL/17
Philips Semiconductors
TDA8757A
Triple 8-bit ADC 205 Msps
Preliminary data
Rev. 01 — 22 March 2002
19 of 37
9397 750 09549
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
To modulate this gain, the ne register is programmed using the above equation. With
a full-scale ADC input, the ne register resolution is a 1
2 LSB peak-to-peak (see
Table 7 for NCOARSE = 32).
The default programmed value is: NFINE =0.
9.1.4
Control register
COAST and HSYNC signals can be derived by setting the I2C-bus control bits ‘Vlevel’
and ‘Hlevel’ respectively. When bits ‘Vlevel’ and ‘Hlevel’ are set to zero, COAST and
HSYNC are active HIGH.
Bit ‘Edge’ denes the rising or falling edge of CKREF to synchronize the PLL. It will
be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1.
Bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These bits
have to be logic 0 during normal use.
Bit ‘Cken’ is used for the test to check the CKADC internal signal. This bit has to be
logic 0 during normal use.
Bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the bandwidth of
the PLL, as shown in Table 8.
The default programmed value is as follows:
Charge pump current = 700 A
Bits ‘Up’ and ‘Do’ are used for testing, normally they are set to logic 0
Rising edge of CKREF: bit ‘Edge’ at logic 0
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
Table 7:
Typical gain correspondence (FINE)
NFINE
Gain
Vi to be full-scale (V)
0
0.825
1.212
31
0.878
1.139
Table 8:
Charge pump current control
Ip2
Ip1
Ip0
Current (
A)
0
6.25
0
1
12.5
01025
01150
100100
101200
110400
111700
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