參數(shù)資料
型號: TDA8020
廠商: NXP Semiconductors N.V.
英文描述: Dual smart card interface
中文描述: 雙界面智能卡
文件頁數(shù): 17/24頁
文件大?。?/td> 114K
代理商: TDA8020
2001 Aug 15
17
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
Notes
1.
Two ceramic multilayer capacitors of minimum 100 nF with low ESR should be used in order to meet these
specifications.
Pin I/O1 has an internal 15 k
pull-up resistor to V
CC1
and pin I/O2 has an internal 15 k
pull-up resistor to V
CC2
.
Pins I/O1uC and I/O2uC have an internal 22 k
pull-up resistor to V
DDI
.
2.
3.
Clock inputs (pins CLKIN1 and CLKIN2)
f
ext
external frequency applied
on CLKIN1 and CLKIN2
LOW-level input voltage
HIGH-level input voltage
input transition times
0
25
MHz
V
IL
V
IH
t
i(r)
, t
i(f)
Logic inputs (pins SAD0 and SAD1)
0
0.7V
DDI
0.25V
DDI
V
DDI
+ 0.3
100
V
V
ns
V
IL
V
IH
I
LIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input leakage
current
HIGH-level input leakage
current
input capacitance
0.3
0.7V
DDI
0.25V
DDI
V
DDI
+ 0.3
±
20
V
V
μ
A
I
LIH
±
20
μ
A
C
i
Interrupt line (pin IRQ; open-drain; active LOW output)
10
pF
V
OL
I
LH
Serial data input/output (pin SDA; open-drain)
LOW-level output voltage
HIGH-level leakage current
I
o
= 2 mA
0.3
10
V
μ
A
V
IL
V
IH
I
LH
I
IL
V
OL
Serial clock input (pin SCL; open-drain)
LOW-level input voltage
HIGH-level input voltage
HIGH-level leakage current
LOW-level input current
LOW-level output voltage
0.3
0.7V
DDI
0.25V
DDI
V
DDI
+ 0.3
1
0.3
V
V
μ
A
depends on the pull-up resistance
I
OL
= 3 mA
V
V
IL
V
IH
I
LH
I
IL
LOW-level input voltage
HIGH-level input voltage
HIGH-level leakage current
LOW-level input current
0.3
0.7V
DDI
0.25V
DDI
V
DDI
+ 0.3
1
V
V
μ
A
depends on the pull-up resistance
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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