參數(shù)資料
型號(hào): TDA8020
廠商: NXP Semiconductors N.V.
英文描述: Dual smart card interface
中文描述: 雙界面智能卡
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 114K
代理商: TDA8020
2001 Aug 15
15
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
Clock output to the cards (pins CLK1 and CLK2)
V
o(inactive)
output voltage in inactive
mode
no load
I
inactive
= 1 mA
pin grounded
0
0
0
0.1
0.3
1
V
V
mA
I
inactive
current from pin CLK when
inactive
LOW-level output voltage
HIGH-level output voltage
rise time
fall time
clock frequency
V
OL
V
OH
t
r
t
f
f
clk
I
OL
= 200
μ
A
I
OH
<
200
μ
A
C
L
= 30 pF
C
L
= 30 pF
1 MHz Idle configuration
operational
C
L
= 30 pF
C
L
= 30 pF
0
V
CC
0.5
1
0
45
0.2
0.3
V
CC
8
8
1.5
10
55
V
V
ns
ns
MHz
MHz
%
V/ns
δ
SR
duty factor
slew rate (rise and fall)
Data lines (pins I/O1 and I/O2);
note 2
V
o(inactive)
output voltage in inactive
mode
no load
I
inactive
= 1 mA
pin grounded
0
0.1
0.3
1
V
V
mA
I
inactive
current from pin I/O when
inactive
LOW-level output voltage
HIGH-level output voltage
V
OL
V
OH
I
OL
= 1 mA
no DC load
I
OH
<
20
μ
A
I
OH
<
40
μ
A
V
OH
= 0.9V
CC
; C
L
= 80 pF
0
0.9V
CC
0.8V
CC
0.75V
CC
1
0.3
V
CC
+ 0.1
V
CC
+ 0.1
V
CC
+ 0.1
V
V
V
V
mA
I
edge
current from pins I/O1
and I/O2 when active pull-up
delay between falling edge
on pins I/O1, I/O2, I/O1uC,
I/O2uC and width of active
pull-up pulse
LOW-level input voltage
HIGH-level input voltage
LOW-level input current on
pin I/O
HIGH-level input leakage
current on pin I/O
input transition times
output transition times
t
d(edge)
500
650
ns
V
IL
V
IH
I
IL
0.3
1.5
+0.8
V
CC
600
V
V
μ
A
V
IL
= 0
I
LIH
V
IH
= V
CC
10
μ
A
t
i(r)
, t
i(f)
t
o(r)
, t
o(f)
from V
IL(max)
to V
IH(min)
C
L
< 80 pF; no DC load;
10% to 90% from 0 to
V
CC1
and V
CC2
1.5
0.1
μ
s
μ
s
C
i
input capacitance on
pins I/O1 and I/O2
internal pull-up resistance
between pin I/O and V
CC
10
pF
R
pu(int)
12
15
18
k
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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