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參數(shù)資料
| 型號(hào)： | TDA7546 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multichip module for TMC tuner applications |
| 中文描述： | 豐田汽車多芯片模塊調(diào)諧器應(yīng)用 |
| 文件頁(yè)數(shù)： | 65/68頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | TDA7546 |
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TDA7546
Application notes
65/68
8
Application notes
8.1
Typical RDS data transfer:
1.
After power up the device, the PLL must be initialized and enabled to generate the 8.55
MHz or 8.664 MHz system clock (fsys). If the XTI frequency is already 8.55 MHz or
8.664 MHz, this point can be skipped. If not, the pllreg4-0 register must be programmed
via I
2
C/SPI. If the XTI frequency is smaller then 8.55 MHz, the reduced maximum
I
2
C/SPI speed must be considered. After the pllreg4-0 register has been programmed,
500 us and additional 25 XTI input clock cycles must be waited until the PLL is locked
and the system clock fsys is switched over to the PLL output clock. Then the next
I
2
C/SPI transfer is allowed with its maximum speed specified for the 8.55/8.664 MHz
system clock (fsys).
In the next I
2
C/SPI transfer the interrupt source will be set to “buffer not empty”
(itsrc[2:0] = 001) and a resynchronization should be forced (rds_int[5] = 1), to be sure
that the buffer is empty and not filled with spurious RDS data. To do this only an write
access to the first register rds_int is needed.
Now the pin INTN must be continuously checked for an interrupt (active low). If there is
an interrupt the five registers rds_int, rds_qu, rds_corrp, rds_bd_h and rds_bd_l must
be read out to get the RDS data. The next interrupt can not be expected before 22 ms.
If it is not possible to service the interrupt in time, then the RDS buffer can store up to
24 RDS bocks. If the buffer is full and the data could not be read before the next RDS
block, the “buffer overflow” flag (rds_corrp[0] = 1) will be set. In this case at least one
RDS block is missed. The “buffer overflow” flag is only cleared, if the whole RDS buffer
is read out.
2.
3.
4.
If there is no pin available for checking the INTN pin, then it is possible to read out the RDS
data by I
2
C/SPI polling. Only the “buffer not empty” flag (rds_int[6]) can be used for that. If
rds_int[6] bit is set, the I
2
C/SPI transfer must be continued, until at least the four register
rds_qu, rds_corrp, rds_bd_h and rds_bd_l are read out.
This must be done until rds_int[6] bit is set to zero (last RDS block). It is possible that the last
RDS block is the same as the last but one RDS block. This is the case if just one RDS block
was stored in the RAM buffer. If they are identical, one of them can be skipped.
If another interrupt source is used instead of “buffer not empty” for the INTN pin, also the
polling mode must be used for reading out the whole RDS buffer, as described above.
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PDF描述 |
|---|---|
| TDA7546TR | Multichip module for TMC tuner applications |
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| TDA7550R | DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND AUDIO APPLICATIONS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA7546TR | 制造商:STMicroelectronics 功能描述: |
| TDA7548 | 功能描述:音頻放大器 4 x 50W Multi Quad Power Amplifer D RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TDA7550 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TDA7550R | 制造商:STMicroelectronics 功能描述: |
| TDA7551 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND AUDIO APPLICATIONS |
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