參數(shù)資料
型號： TCS59SM816BFTL-75
廠商： Toshiba Corporation
英文描述： 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
中文描述： 4米× 4Banks × 16位同步DRAM（4組4米× 16位同步動態(tài)RAM）的
文件頁數(shù)： 40/49頁
文件大?。?/td> 2423K
代理商： TCS59SM816BFTL-75
TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 40/49
8. Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. Auto Refresh is
similar to the CAS -before-RAS refresh of conventional DRAMs and is performed by issuing the Auto Refresh
command while all banks are in the idle state. By repeating the Auto Refresh cycle, all banks refreshed
automatically. The Refresh operation must be performed 8192 times (rows) within 64 ms (Figure 11). The period
between the Auto Refresh command and the next command is specified by t
RC
.
Self Refresh mode is entered by issuing the Self Refresh command (CKE asserted “l(fā)ow”) while all banks are in
the idle state. The device is in Self Refresh mode for as long as CKE is held “l(fā)ow”. In Self Refresh mode, all
input/output buffers (except the CKE buffer) are disabled to lower power dissipation (Figure 12).
In the case of 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed
within 15.6
μ
s before entering and after exiting the Self Refresh mode.
In the case of distributed Auto Refresh commands, distributed Auto Refresh commands must be issued every
15.6
μ
s and the last distributed Auto Refresh command must be performed within 15.6
μ
s before entering the
Self Refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within
15.6
μ
s.
9. Power Down Mode
When the device enters the Power Down mode, all input/output buffers (except CKE buffer) are disabled to
lower power dissipation in the idle state. Power Down mode is entered by asserting CKE “l(fā)ow” while the device
is not running a Burst cycle. Taking CKE “high” exit this mode. When CKE goes high, a No-operation command
must be input at next CLK rising edge of CLK (Figure 13).
10. CLK suspension and Input/Output Mask
When the device is running a Burst cycle, the internal CLK is suspended by asserting CKE “l(fā)ow” the burst
operation is frozen from the next cycle. A Read/Write operation is held intact until the CKE signal is taken
“high”.
The Output Disable/Write Mask signal (DQM) has two functions, controlling the output data in a Read cycle
and performing word mask in a Write cycle. When the DQM is asserted “high” at the positive edge of CLK, the
output data is disabled after two clock cycles in the case of a Read operation and the write data is masked at the
same clock cycle in the case of a Write operation. The timing relations between the CKE timing and DQM are
described in Figure 21 (a) and 21 (b).
相關(guān)PDF資料
PDF描述
TCS59SM816BFTL-80 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
TCS800 800 Watts, 50 Volts, Pulsed Avionics 1030 MHz
TD-76 MICROWAVE NOISE TUBES & NOISE SOURCES
TD-10 MICROWAVE NOISE TUBES & NOISE SOURCES
TD-11 MICROWAVE NOISE TUBES & NOISE SOURCES
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