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參數(shù)資料
| 型號： | TCS59SM816BFTL-70 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM) |
| 中文描述： | 4米× 4Banks × 16位同步DRAM（4組4米× 16位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 37/49頁 |
| 文件大?。?/td> | 2423K |
| 代理商： | TCS59SM816BFTL-70 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 37/49
7. Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into
three fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate
the column access sequence in a Burst cycle, and a Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state.
The data to be set in the Mode Register is transferred using the A0~A11 address inputs. The initial value of the
Mode Register after power-up is undefined; therefore the Mode Register Set command must be issued before
proper operation.
Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be
1, 2, 4, 8, words, or full-page.
A2
A1
A0
Burst Length
0
0
0
1 word
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
1
1
Full-Page
Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0,
Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected.
Both Addressing modes support burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports
the full-page burst.
A3
Addressing Mode
0
Sequential
1
Interleave
CAS
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