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參數(shù)資料
| 型號： | TAS3218IPZPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 61/79頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | TAS3218IPZPR |
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Load Memory Control and Data Register (0x04 and 0x05)
SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com
Bits 4032 define the memory load error status on EEPROM download and slave download.
Table 26. Analog Busy(1)
ANALOG BUSY FLAG
ABSY
Analog is busy
1
Analog not busy
0
(1)
Default values are shown in italics.
Analog control sequence takes time (maximum around 500 ms for headphone power up). This busy flag indicate
whether analog control sequence is running or not.
Table 27. I2C Bus Error(1)
I2C BUS ERROR
BUSE
Bus error
1
No bus error
0
(1)
Default values are shown in italics.
If I2C bus error occurs, this flag will be set. Only host uC can clear this flag by writing 0 to this bit. I2C bus error
status is read from ESFR (0xC5, bit 6), and is cleared by ESFR (0xC7, bit 6).
The I2C Memory Load port permits the system controller to load the TAS3218 memories as an alternative to
having the TAS3218 load its memory from an external EEPROM.
The transfer is performed by writing to two I2C registers. The first register is a eight byte register than holds the
check sum, the memory to be written, the starting address, the number of data bytes to be transferred. The
second register holds eight bytes of data.
The memory load operation starts with the first register being set. Then the data is written into the second
register using the format shown. After the last data byte is written into the second register, an additional two
bytes are written which constrain the two byte checksum. At that point, the transfer is complete and status of the
operation is reported in the status register.
NOTE:
Once the micro program memory has been loaded, further updates to this memory
are inhibited until the device is RESET.
When the first I2C slave down load register is written by the system controller the TAS3218 will update the status
register by setting a error bit to indicate an error for the memory type that is being loaded. This error bit is reset
when the operation complete and a valid checksum has been received.
For example when the Micro program memory is being loaded, the TAS3218 will set a Micro program memory
error indication in the status register at the start of the sequence. When the last byte of the micro program
memory and checksum is received, the TAS3218 will clear the micro program memory error indication. This
enables the TAS3218 to preserve any error status indications that occur as a result of incomplete transfers of
data/ checksum error during a series of data and program memory load operations.
The checksum is always contained in the last two bytes of the data block.
The I2C slave download is terminated when a termination header with a zero length byte count filed is received.
64
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS3218
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