參數(shù)資料
型號(hào)： TAS3218IPZPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, TQFP-100
文件頁數(shù)： 25/79頁
文件大小： 1263K
代理商： TAS3218IPZPR
I2C Master Mode Operation
Stop
Condition
Acknowledge
I C Device Address
and
2
Read/Write Bit
I C Device Address
and
2
Read/Write Bit
Sub Address
First Data Byte
Other Data Bytes
Last Data Byte
Acknowledge
Not
Acknowledge
A7
SS
A0
D0
Ack
R/W Ack
D7
D0
Ack
D0
SS
A6
Ack
A6
SS
A0
SS
R/W Ack
Start
Condition
Repeat Start
Condition
www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008
If the master device issues more data received acknowledges than required to receive the data for a given sub
address, the master device simply receives complete or partial sets of data, depending on how many data
received acknowledges are issued from the sub address(es) that follow. I2C read transactions, both sequential
and random, can impose wait states.
For the standard I2C mode (SCL = 100 kHz), worst-case wait state times for an 8-MHz microprocessor clock is
on the order of 2 s. Nominal wait state times for the same 8-MHz microprocessor clock is on the order of 1 s. For
the fast I2C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait state times can
extend up to 10.5 s in duration. Nominal wait state times for this same case lie in a range from 2 s to 4.6 s.
Increasing the microprocessor clock frequency lowers the wait state times and for the standard I2C mode, a
higher microprocessor clock can totally eliminate the presence of wait states.
For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I2C mode,
higher microprocessor clocks shortens the wait state times encountered, but does not totally eliminate their
presence.
I2C master mode operation is enabled following a reset or power on reset.
The TAS3218 uses the master mode to download from EEPROM the memory contents for the following.
Micro program memory
Micro extended memory
DSP program memory
DSP coefficient memory
DSP data memory
The TAS3218, when operating as an I2C master, can execute a complete download of any internal memory or
any section of any internal memory without requiring any wait states.
When the TAS3218 operates as an I2C master, it generates a repeated start without an intervening stop
command while downloading program and memory DATA from an external EEPROM. When a repeated start is
sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to quickly transfer large blocks
of data.
Figure 22. Multiple Byte Read Transfer
The TAS3218 will query the bus for an I2C EEPROM at an address 1010xxx. The value xxx can be chip selects,
other information, or dont cares depending on the EEPROM selected.
The first act of the TAS3218 as master will be to transmit a start condition along with the device address of the
I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address
byte, and the TAS3218 send a sub address byte, which the EEPROM will acknowledge. Most EEPROMs have at
least 2-byte addresses and will acknowledge as many as are appropriate. At this point, the EEPROM sends a
last acknowledge and becomes a slave transmitter. The TAS3218 acknowledges each byte repeatedly to
continue reading each data byte that is stored in memory.
Copyright 2008, Texas Instruments Incorporated
31
Product Folder Link(s): TAS3218
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