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參數(shù)資料
| 型號(hào)： | T90FJR |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Dual Common Interface Hardware Controller- CIMax |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 617K |
| 代理商： | T90FJR |
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9
T90FJR
Rev. A
–
7-Sep-01
Universal Control Signal
Generator (UCSG)
CIMaX
can be connected to various CPUs, each of them having a different external
bus control structure with different signals and timings. To interface with a large number
of different microprocessors, the host microprocessor interface includes a fully config-
urable UCSG block that generates the right PCMCIA control signals.
At reset, the host microprocessor interface is disabled ; CS, RD/DIR and WR/STR
inputs are inactive and WAIT/ACK and INT are in high impedance state. The only avail-
able access is the configuration interface (I2C) which permits to set up the CIMaX
.
Once the proper parameters have been entered in the CIMaX
, the interface is
enabled by setting the LOCK bit in the CIMaX
Control Register (@1Fh). The access
to the modules is then possible and some parameters related to the host microproces-
sor interface are impossible to modify.
Host microprocessor input control signals are CS, RD/DIR, WR/STR and output signals
are WAIT/ACK and INT. Input and output active levels can be individually set up by con-
figuration bits. In addition, the output buffer structure is also configurable to be either
open-drain (allowing wired-or) or push-pull, in the UCSG1 and UCSG2 registers.
CS: Chip select signal indicates to the CIMaX
that the current bus cycle is
addressed to one of the modules (or external device)
RD/DIR: Read strobe or direction signal. This signal function can be chosen with the
RDIR bit. Read strobe indicates a valid read bus cycle or direction signal indicates
the bus transfer direction when a valid bus transfer is indicated by the transfer
strobe signal
WR/STR: Write strobe or transfer strobe. This signal function can be adjusted with
the WSTR bit. Write strobe indicates a valid write bus cycle or transfer strobe
indicates a valid bus transfer in direction indicated by RD/DIR state.
WAIT/ACK: Wait or Acknowledge transfer. In WAIT mode, this signal inserts wait
cycles in the bus read or write operation in process. In ACK mode, this signal
indicates the completion of the bus cycle.
INT: Interrupt output to the host microprocessor.
The UCSG (universal control signals generator) inputs the RD / DIR, WR / STR and CS
signals from host microprocessor, WAITA# and WAITB# from the modules and gener-
ates all the control signals to modules, host microprocessor, buffers and external
device : CE1A#, CE2A#, CE1B#, CE2B#, REG#, OE#, WE#, IORD#, IOWR#, WAIT,
ACK, ADLE, ADOE#, DATDIR, DATOE#.
The input signals from the host microprocessor are combined, depending on the host
microprocessor configuration, to form a read and write signal RD
’
and WR
’
. These sig-
nals indicate an active read or write cycle in process.
Setup time before a stop condition
t
SU,STO
0.6
μs
Capacitive load for each bus line
C
b
400
pF
Parameter
Symbol
Min
Max
Unit
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