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參數(shù)資料
| 型號： | T90FJR |
| 廠商： | ATMEL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Common Interface Hardware Controller- CIMax |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 11/41頁 |
| 文件大?。?/td> | 617K |
| 代理商： | T90FJR |
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11
T90FJR
Rev. A
–
7-Sep-01
(1) these timings are given for a load of 50 pF on WAIT/ACK pin.
(1) 1.5 cycle corresponds to the start cycle detection time. t1 depends actually on the previous cycle completion which
depends on t8 and t10 read timings. So t1 ranges from 3.5 to 6.5 cycles.
Note:
t0: delay between start of a read cycle and activation of WAIT
t1: delay between start of a read cycle and falling edge of CE and REG# (if required for
the current cycle)
t2: delay between start of a read cycle and falling edge of OE# (and switching of the data
buffer direction control)
t3: delay between falling edge of CE and falling edge of OE# (and switching of the data
buffer direction control)
t4: read cycle length. This time is the necessary delay for the module to present the read
data on the data output bus. After t4 delay is expired, WAIT is deasserted and ACK
asserted thus enabling the processor to read the data on the bus. At the same time,
ADLE is reset to latch the address presented to the module so that the data is not
changed while the processor is reading. t4 can be lengthened by the module if the mod-
ule requires extra wait cycles by asserting its WAIT# pin low.
t5: delay to deassertion of module read signal (OE# or IORD#) after minimum delay after
t4.
t6: delay between end of read cycle indicated by the processor and data bus isolation
(DATOE# asserted)
t7: delay between data bus isolation and switching back of the data bus direction
t8: delay to deassertion of module read signal (OE# or IORD#) after end of a read cycle
by the processor.
t9: delay between deassertion of the module read signal and deassertion of CE, REG#
and ADLE (releasing the address bus)
t10: delay between deassertion of the module read signal and re-enabling of the data
bus (see t7 on write cycle)
Memory read
IO, EC,
Ext
600ns
300 ns
250n
s
200ns
150
ns
100
ns
t0
max
(1)
26 ns
t1 max
1.5 cycle + 26 ns
(2)
t2 min
3
1
1
1
1
1
2
t3
3
1
1
1
1
1
2
t4
14
8
7
5
4
3
3
t5 min
0
2
t6
max
(1)
26 ns
t7 min
0 ns
t7 max
70 ns
t8 max
1.5 cycle + 26 ns
t9
1
1
1
1
1
1
1
t10 min
5
3
3
3
3
2
2
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