參數(shù)資料
型號: T9000
廠商: Lineage Power
英文描述: ISDN Network Termination Node (NTN) Device(ISDN網(wǎng)絡(luò)終端節(jié)點器件)
中文描述: ISDN網(wǎng)絡(luò)終端節(jié)點(新界西)設(shè)備(ISDN網(wǎng)網(wǎng)絡(luò)終端節(jié)點器件)
文件頁數(shù): 62/126頁
文件大小: 1523K
代理商: T9000
62
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
9 HDLC with FIFO Module
(continued)
9.5 HDLC Register Set
(continued)
Table 62. HTXL: HDLC Transmit Data Last Byte (0x1F)
Table 63. HRX: HDLC Receive Data (0x20)
Table 64. HSCR: HDLC SAPI C/R Bit Mask (0x21)
Reg
HTXL
RESET
R/W
W
Default
Bit 7
TXDL7
Bit 6
TXDL6
Bit 5
TXDL5
Bit 4
TXDL4
Bit 3
TXDL3
Bit 2
TXDL2
Bit 1
TXDL1
Bit 0
TXDL0
Bit #
7—0
Symbol
TXDL[7:0]
Name/Description
HDLC Transmit Data—Last Byte.
The last data byte of each transmitted packet is writ-
ten to this register (rather than HTX) to indicate to the transmitter that this is the end of
the packet. This register occupies the same physical space as HTX (i.e., it maps to the
transmit FIFO).
Reg
HRX
RESET
R/W
R
Default
Bit 7
RXD7
Bit 6
RXD6
Bit 5
RXD5
Bit 4
RXD4
Bit 3
RXD3
Bit 2
RXD2
Bit 1
RXD1
Bit 0
RXD0
Bit #
7—0
Symbol
RXD[7:0]
Name/Description
Received Data/Status.
The content of the FIFO is read when addressing this register.
The first received bit is the least significant bit of this byte.
Reg
HSCR
RESET
R/W
R/W
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
S3CRE
0
Bit 2
S2CRE
0
Bit 1
S1CRE
0
Bit 0
S0CRE
0
Bit #
7—4
3
Symbol
Name/Description
Reserved.
Program to 0.
SAPI3 Command/Response Bit Comparison Enable.
S3CRE
0: SAPI3 C/R bit is ignored.
1: SAPI3 comparison includes C/R bit (HSM3.1).
SAPI2 Command/Response Bit Comparison Enable.
2
S2CRE
0: SAPI2 C/R bit is ignored.
1: SAPI2 comparison includes C/R bit (HSM2.1).
SAPI1 Command/Response Bit Comparison Enable.
1
S1CRE
0: SAPI1 C/R bit is ignored.
1: SAPI1 comparison includes C/R bit (HSM1.1).
SAPI0 Command/Response Bit Comparison Enable.
0
S0CRE
0: SAPI0 C/R bit is ignored.
1: SAPI0 comparison includes C/R bit (HSM0.1).
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