參數(shù)資料
型號(hào)： T9000
廠商： Lineage Power
英文描述： ISDN Network Termination Node (NTN) Device(ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)器件)
中文描述： ISDN網(wǎng)絡(luò)終端節(jié)點(diǎn)（新界西）設(shè)備（ISDN網(wǎng)網(wǎng)絡(luò)終端節(jié)點(diǎn)器件）
文件頁(yè)數(shù)： 4/126頁(yè)
文件大小： 1523K
代理商： T9000
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4
Lucent Technologies Inc.
Advance Data Sheet
April 2000
ISDN Network Termination Node (NTN) Device
T9000
Table of Contents
(continued)
Tables
Page
Table 60. HRDA: HDLC Receive FIFO Data
Available (0x1D) ....................................................61
Table 61. HTX: HDLC Transmit Data (0x1E) ..........61
Table 62. HTXL: HDLC Transmit Data Last Byte
(0x1F) ....................................................................62
Table 63. HRX: HDLC Receive Data (0x20) ...........62
Table 64. HSCR: HDLC SAPI C/R Bit Mask
(0x21) ....................................................................62
Table 65. HSM0: HDLC SAPI Match Pattern 0
(0x22) ....................................................................63
Table 66. HTM0: HDLC TEI Match Pattern 0
(0x23) ....................................................................63
Table 67. HSM1: HDLC SAPI Match Pattern 1
(0x24) ....................................................................63
Table 68. HTM1: HDLC TEI Match Pattern 1
(0x25) ....................................................................64
Table 69. HSM2: HDLC SAPI Match Pattern 2
(0x26) ....................................................................64
Table 70. HTM2: HDLC TEI Match Pattern 2
(0x27) ....................................................................64
Table 71. HSM3: HDLC SAPI Match Pattern 3
(0x28) ....................................................................64
Table 72. HTM3: HDLC TEI Match Pattern 3
(0x29) ....................................................................65
Table 73. HSMOD: HDLC SAPI Modifier Register
(0x2A) ....................................................................65
Table 74. HTMOD: HDLC TEI Modifier Register
(0x2B) ....................................................................66
Table 75. HIR: HDLC Interrupt Register (0x2C) ......67
Table 76. HIE: HDLC Interrupt Enable 15 (0x2D) ...68
Table 77. GCI+ Interface Signals ............................69
Table 78. TDM Data Rate and Clock Options ..........70
Table 79. GCI-TE Data-Slot Association ..................76
Table 80. GCCF: GCI+ Configuration Register
(0x2E) ...................................................................79
Table 81. GCOF1: GCI PFS1 Offset Select
(0x2F) ....................................................................80
Table 82. GCOF2: GCI PFS2 Offset Select
(0x30) ....................................................................80
Table 83. GCDMD: GCI Downstream (Transmit)
Monitor Data (0x31) ..............................................81
Table 84. GCDML: GCI Downstream (Transmit)
Monitor Data Last (0x32) ......................................81
Table 85. GCUMD: GCI Upstream (Receive) Monitor
Data (0x33) ...........................................................81
Table 86. GCDCI: GCI Downstream (Transmit) C/I
Data (0x34) ...........................................................82
Table 87. GCUCI: GCI Upstream (Receive) C/I
Data (0x35) ...........................................................82
Table 88. GCIR: GCI Interrupt Register (0x36) .......83
Table 89. GCIE: GCI Interrupt Enable (0x37) ..........84
Table 90. GPDIR0: GPIO Port 0 Pin Direction
(0x38) ....................................................................86
Tables
Page
Table 91. GPDIR1: GPIO Port 1 Pin Direction
(0x39) ................................................................... 87
Table 92. GPDIR2: GPIO Port 2 Pin Direction
(0x3A) .................................................................. 87
Table 93. GPAF0: GPIO Alternate Function
Register #0 (0x3B) ............................................... 88
Table 94. GPAF1: GPIO Alternate Function
Register #1 (0x3C) ............................................... 89
Table 95. GPD0: GPIO Port 0 Data Register
(0x3D) .................................................................. 89
Table 96. GPD1: GPIO Port 1 Data Register
(0x3E) .................................................................. 90
Table 97. GPD2: GPIO Port 2 Data Register
(0x3F) ................................................................... 90
Table 98. GPLEI: GPIO Level-Edge-Triggered
Interrupt Control (0x40) ........................................ 90
Table 99. GPPOL: GPIO Interrupt Polarity
Control (0x41) ...................................................... 91
Table 100. GPIR: GPIO Interrupt Register
(0x42) ................................................................... 91
Table 101. GPIE: GPIO Interrupt Enable
(0x43) ................................................................... 92
Table 102. ROM Code ............................................. 96
Table 103. PWM Sine Modulator Programming
Example ............................................................... 98
Table 104. PW0CF: Pulse-Width Modulator 0
Configuration (0x44) .......................................... 100
Table 105. PW0VH: Pulse-Width Modulator 0
Pulse-Width Value, High Byte (0x45) ................. 101
Table 106. PW0VL: Pulse-Width Modulator 0
Pulse-Width Value, Low Byte (0x46) ................. 101
Table 107. PW1CF: Pulse-Width Modulator 1
Configuration (0x47) .......................................... 102
Table 108. PW1VH: Pulse-Width Modulator 1
Pulse-Width Value, High Byte (0x48) ................. 103
Table 109. PW1VL: Pulse-Width Modulator 1
Pulse-Width Value, Low Byte (0x49) ................. 103
Table 110. PWIR: Pulse-Width Modulator Interrupt
Register (0x4A) .................................................. 103
Table 111. DCCF: dc/dc Configuration Register
(0x4B) ................................................................ 104
Table 112. Comparator Characteristics ................ 106
Table 113. CME: Comparator Enable (0x4C) ....... 106
Table 114. CMT: Comparator Transition Polarity
(0x4D) ................................................................ 106
Table 115. CMIR: Comparator Interrupt Register
(0x4E) ................................................................ 107
Table 116. CMIE: Comparator Interrupt Enable
(0x4F) ................................................................. 107
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